| Reconfigured scan forest for test application cost, test data volume, and test power reduction D Xiang, K Li, J Sun, H Fujiwara IEEE Transactions on Computers 56 (4), 557-562, 2007 | 74 | 2007 |
| Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests D Xiang, K Li, H Fujiwara, J Sun 2006 International Conference on Computer Design, 446-451, 2006 | 13 | 2006 |
| Constraining transition propagation for low-power scan testing using a two-stage scan architecture D Xiang, K Li, H Fujiwara, K Thulasiraman, J Sun IEEE Transactions on Circuits and Systems II: Express Briefs 54 (5), 450-454, 2007 | 10 | 2007 |
| Fast and effective fault simulation for path delay faults based on selected testable paths D Xiang, Y Zhao, K Li, H Fujiwara 2007 IEEE International Test Conference, 1-10, 2007 | 3 | 2007 |
| A Two-stage Scan Architecture for Cost-Effective Scan Testing D Xiang, KW Li CHINESE JOURNAL OF COMPUTERS-CHINESE EDITION- 29 (5), 786, 2006 | 2 | 2006 |
| Scan-based BIST using an improved scan forest architecture D Xiang, K Li, M Chen, Y Wu 13th Asian Test Symposium, 88-93, 2004 | 2 | 2004 |
| 路径延迟故障测试向量压缩方法及装置 D Xiang, K Li CN Patent 2,008,100,566,767, 2008 | | 2008 |
| Computer Aided Design and Electronic Design Automation-Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture D Xiang, K Li, H Fujiwara, K Thulasiraman, J Sun IEEE Transactions on Circuits and Systems-II-Express Briefs 54 (5), 450-454, 2007 | | 2007 |
| 构造具有低测试功耗的两级扫描测试结构的方法 D Xiang, K Li, J Sun CN Patent 2,004,100,888,813, 2004 | | 2004 |
| 构造无故障屏蔽奇偶测试的扫描链和扫描森林的方法 D Xiang, K Li, J Sun CN Patent 2,004,100,096,782, 2004 | | 2004 |
Hideo Fujiwara 藤原秀雄Professor Emeritus, NAIST在 fujiwaralab.net 的电子邮件经过验证
Hideo Fujiwara 藤原秀雄Professor Emeritus, NAIST在 fujiwaralab.net 的电子邮件经过验证
K. ThulasiramanUniversity of Oklahoma在 ou.edu 的电子邮件经过验证