| A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure CC Liu, SJ Chang, GY Huang, YZ Lin IEEE Journal of Solid-State Circuits 45 (4), 731-740, 2010 | 1454 | 2010 |
| A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation CC Liu, SJ Chang, GY Huang, YZ Lin, CM Huang, CH Huang, L Bu, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 386-387, 2010 | 369 | 2010 |
| A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process CC Liu, SJ Chang, GY Huang, YZ Lin 2009 symposium on VLSI circuits, 236-237, 2009 | 188 | 2009 |
| A 1-µW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications GY Huang, SJ Chang, CC Liu, YZ Lin IEEE Journal of Solid-State Circuits 47 (11), 2783-2795, 2012 | 183 | 2012 |
| A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18 µm CMOS CC Liu, SJ Chang, GY Huang, YZ Lin, CM Huang 2010 Symposium on VLSI Circuits, 241-242, 2010 | 183 | 2010 |
| 10-bit 30-MS/s SAR ADC using a switchback switching method GY Huang, SJ Chang, CC Liu, YZ Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (3), 584-588, 2012 | 121 | 2012 |
| A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS YZ Lin, CC Liu, GY Huang, YT Shyu, YT Liu, SJ Chang IEEE Transactions on Circuits and Systems I: Regular Papers 60 (3), 570-581, 2013 | 92 | 2013 |
| Effective and efficient approach for power reduction by using multi-bit flip-flops YT Shyu, JM Lin, CP Huang, CW Lin, YZ Lin, SJ Chang IEEE transactions on very large scale integration (vlsi) systems 21 (4), 624-635, 2012 | 88 | 2012 |
| Efficient four-coil wireless power transfer for deep brain stimulation CL Yang, CK Chang, SY Lee, SJ Chang, LY Chiou IEEE Transactions on Microwave Theory and Techniques 65 (7), 2496-2507, 2017 | 80 | 2017 |
| A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS YZ Lin, CC Liu, GY Huang, YT Shyu, SJ Chang 2010 Symposium on VLSI Circuits, 243-244, 2010 | 73 | 2010 |
| An asynchronous binary-search ADC architecture with a reduced comparator count YZ Lin, SJ Chang, YT Liu, CC Liu, GY Huang IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 1829-1837, 2010 | 71 | 2010 |
| A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme YZ Lin, CW Lin, SJ Chang IEEE Transactions on very large scale integration (VLSI) systems 18 (3), 509-513, 2009 | 70 | 2009 |
| A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS YZ Lin, SJ Chang, YT Liu, CC Liu, GY Huang 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 58 | 2009 |
| A histogram-based testing method for estimating A/D converter performance HW Ting, BD Liu, SJ Chang IEEE Transactions on Instrumentation and Measurement 57 (2), 420-427, 2008 | 54 | 2008 |
| Mismatch-aware common-centroid placement for arbitrary-ratio capacitor arrays considering dummy capacitors CW Lin, JM Lin, YC Chiu, CP Huang, SJ Chang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 44 | 2012 |
| A 10b 200MS/s 0.82 mW SAR ADC in 40nm CMOS GY Huang, SJ Chang, YZ Lin, CC Liu, CP Huang 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 289-292, 2013 | 42 | 2013 |
| An efficient design-for-testability scheme for motion estimation in H. 264/AVC TH Wu, YL Tsai, SJ Chang 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2007 | 39 | 2007 |
| Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits CW Lin, JM Lin, YC Chiu, CP Huang, SJ Chang Proceedings of the 48th Design Automation Conference, 528-533, 2011 | 38 | 2011 |
| A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique JF Lin, SJ Chang, CC Liu, CH Huang IEEE Transactions on Circuits and Systems II: Express Briefs 57 (3), 163-167, 2010 | 37 | 2010 |
| Low-power and wide-bandwidth cyclic ADC with capacitor and opamp reuse techniques for CMOS image sensor application JF Lin, SJ Chang, CF Chiu, HH Tsai, JJ Wang IEEE Sensors Journal 9 (12), 2044-2054, 2009 | 37 | 2009 |
