| A Power Optimized Continuous-Time ADC for Audio Applications S Pavan, N Krishnapura, R Pandarinathan, P Sankar IEEE Journal of Solid-State Circuits 43 (2), 351-360, 2008 | 158 | 2008 |
| A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS N Krishnapura, PR Kinget IEEE Journal of Solid-State Circuits 35 (7), 1019-1024, 2000 | 150 | 2000 |
| System and method for orthogonal frequency division multiplexed optical communication I Shpantzer, Y Meiman, M Tseytlin, O Ritterbush, A Salamon, P Feldman, ... US Patent 7,076,169, 2006 | 97 | 2006 |
| A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 m CMOS I Mondal, N Krishnapura IEEE Journal of Solid-State Circuits 52 (8), 2180-2193, 2017 | 94 | 2017 |
| Internally varying analog circuits minimize power dissipation Y Tsividis, N Krishnapura, Y Palaskas, L Toth IEEE Circuits and Devices Magazine 19 (1), 63-72, 2003 | 79 | 2003 |
| Hand talk-implementation of a gesture recognizing glove C Preetham, G Ramakrishnan, S Kumar, A Tamse, N Krishnapura 2013 Texas Instruments India Educators' Conference, 328-331, 2013 | 68 | 2013 |
| 26.3 A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS using a 4-port dual-mode resonator for 5G radios A Bhat, N Krishnapura 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 412-414, 2019 | 63 | 2019 |
| A 16 MHz BW 75 dB DR CT ADC Compensated for More Than One Cycle Excess Loop Delay V Singh, N Krishnapura, S Pavan, B Vigraham, D Behera, N Nigania IEEE Journal of Solid-State Circuits 47 (8), 1884-1895, 2012 | 62 | 2012 |
| Glitch-free phase switching synthesizer P Kinget, N Krishnapura US Patent 6,671,341, 2003 | 59 | 2003 |
| A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission N Krishnapura, M Barazande-Pour, Q Chaudhry, J Khoury, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 52 | 2005 |
| Analysis and design of a discrete-time delta-sigma modulator using a cascoded floating-inverter-based dynamic amplifier RSA Kumar, N Krishnapura, P Banerjee IEEE Journal of Solid-State Circuits 57 (11), 3384-3395, 2022 | 49 | 2022 |
| Noise and power reduction in filters through the use of adjustable biasing N Krishnapura, YP Tsividis IEEE Journal of Solid-State Circuits 36 (12), 1912-1920, 2001 | 46 | 2001 |
| Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time Modulators V Singh, N Krishnapura, S Pavan IEEE Transactions on Circuits and Systems II: Express Briefs 57 (9), 676-680, 2010 | 36 | 2010 |
| System and method for code division multiplexed optical communication I Shpantzer, M Tseytlin, Y Achiam, A Salamon, I Smilanski, O Ritterbush, ... US Patent 7,167,651, 2007 | 34 | 2007 |
| Syllabic-companding log domain filters D Frey, YP Tsividis, G Efthivoulidis, N Krishnapura IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 28 | 2001 |
| Low Phase Noise Quadrature LC VCOs A Bhat, N Krishnapura IEEE Transactions on Circuits and Systems I: Regular Papers 65 (7), 2127-2138, 2018 | 25 | 2018 |
| Circuits with dynamic biasing YP Tsividis, N Krishnapura US Patent 6,861,896, 2005 | 25 | 2005 |
| 25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18 µm CMOS S Mukherjee, AN Bhat, KA Shrivastava, M Bonu, B Sutton, V Gopinathan, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 434-435, 2017 | 23 | 2017 |
| A high-IIP3 third-order elliptic filter with current-efficient feedforward-compensated opamps N Krishnapura, A Agrawal, S Singh IEEE Transactions on Circuits and Systems II: Express Briefs 58 (4), 205-209, 2011 | 23 | 2011 |
| Simplified technique for syllabic companding in log-domain filters N Krishnapura, Y Tsividis, DR Frey Electronics Letters 36 (15), 1257-1259, 2000 | 23 | 2000 |
