| OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators C Chen, H Ding, H Peng, H Zhu, R Ma, P Zhang, X Yan, Y Wang, M Wang, ... ESSCIRC 2017-43rd IEEE European solid state circuits conference, 259-262, 2017 | 30 | 2017 |
| COMB-MCM: Computing-on-memory-boundary NN processor with bipolar bitwise sparsity optimization for scalable multi-chiplet-module edge machine learning H Zhu, B Jiao, J Zhang, X Jia, Y Wang, T Guan, S Wang, D Niu, H Zheng, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 25 | 2022 |
| 16.2 A 28nm 53.8 TOPS/W 8b sparse transformer accelerator with in-memory butterfly zero skipper for unstructured-pruned NN and CIM-based local-attention-reusable engine S Liu, P Li, J Zhang, Y Wang, H Zhu, W Jiang, S Tang, C Chen, Q Liu, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 250-252, 2023 | 21 | 2023 |
| OCEAN: An on-chip incremental-learning enhanced artificial neural network processor with multiple gated-recurrent-unit accelerators C Chen, H Ding, H Peng, H Zhu, Y Wang, CJR Shi IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3 …, 2018 | 18 | 2018 |
| A Communication-aware DNN accelerator on ImageNet using in-memory entry-counting based algorithm-circuit-architecture co-design in 65-nm CMOS H Zhu, C Chen, S Liu, Q Zou, M Wang, L Zhang, X Zeng, CJR Shi IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10 (3 …, 2020 | 13 | 2020 |
| A 0.57-gops/dsp object detection pim accelerator on fpga B Jiao, J Zhang, Y Xie, S Wang, H Zhu, X Kang, Z Dong, L Zhang, C Chen Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 10 | 2021 |
| Tanji: A general-purpose neural network accelerator with unified crossbar architecture H Zhu, Y Wang, CJR Shi IEEE Design & Test 37 (1), 56-63, 2019 | 6 | 2019 |
| A 11.6 μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization X Jia, H Zhu, Y Wang, J Zhang, F Lin, X Xiong, D Xu, C Chen, Q Liu 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2816-2820, 2022 | 4 | 2022 |
| Alpine: An agile processing-in-memory macro compilation framework J Zhang, B Jiao, Y Wang, H Zhu, L Zhang, C Chen Proceedings of the 2021 Great Lakes Symposium on VLSI, 333-338, 2021 | 3 | 2021 |
| A 28 nm 81 Kb 59–95.3 TOPS/W 4T2R ReRAM computing-in-memory accelerator with voltage-to-time-to-digital based output K Zhou, X Jia, C Zhao, X Zhang, G Wu, C Mu, H Zhu, Y Ding, C Chen, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (4 …, 2022 | 2 | 2022 |
| An efficient Markov random field based denoising approach for dynamic vision sensor X Cheng, H Zhu, J Liu, M Wang, X Zeng 2021 IEEE 14th International Conference on ASIC (ASICON), 1-4, 2021 | 2 | 2021 |
| Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors B Jiao, H Zhu, J Zhang, S Wang, X Kang, L Zhang, M Wang, C Chen Proceedings of the 2021 on Great Lakes Symposium on VLSI, 241-246, 2021 | 2 | 2021 |
| XNORAM: An efficient computing-in-memory architecture for binary convolutional neural networks with flexible dataflow mapping S Liu, H Zhu, C Chen, L Zhang, CJR Shi 2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020 | 2 | 2020 |
| A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5 D/3D Integration J Liao, B Jiao, J Zhang, S Liu, H Jiang, J Tao, W Jiang, Q Liu, L Zhang, ... 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 1 | 2023 |
| FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer B Jiao, L Xu, X Yu, H Yang, H Zhu, Y Wang, J Zhu, D Wen, L Wang, J Tao, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2024 | | 2024 |
| SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros M Li, H Zhu, S He, H Zhang, J Liao, D Zhai, C Chen, Q Liu, X Zeng, N Sun, ... IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder M Li, H Zhang, S He, H Zhu, H Zhang, J Liu, J Chen, Z Hu, X Zeng, ... 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | | 2024 |
| Automatic Adder Tree Re-Synthesis Tool for Digital Compute-in-Memory Low-Power Optimization W We, S Guo, H Zhang, X Zhong, C Wang, H Zhu, H Tian, X Zeng, ... 2024 2nd International Symposium of Electronics Design Automation (ISEDA …, 2024 | | 2024 |
| ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test H Zhang, H Zhu, S He, M Li, C Wang, X Xiong, H Tian, X Zeng, C Chen 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | | 2024 |
| Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning H Zhu, H Zhang, S He, M Li, X Zeng, C Chen IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
Chixiao ChenAssociate Prof., Fudan University在 fudan.edu.cn 的电子邮件经过验证
