| Offset voltage estimation model for latch-type amplifiers SH Woo, H Kang, K Park, SO Jung IET Circuits, Devices & Systems 4 (6), 503-513, 2010 | 44 | 2010 |
| Process Variation Tolerant All-Digital 90Phase Shift DLL for DDR3 Interface H Kang, K Ryu, DH Jung, D Lee, W Lee, S Kim, J Choi, SO Jung IEEE Transactions on Circuits and Systems I: Regular Papers 59 (10), 2186-2196, 2012 | 30 | 2012 |
| Digital DLL including skewed gate type duty correction circuit and duty correction method thereof W Lee, D Lee, SO Jung, H Kang, K Ryu, D Jung US Patent 8,519,758, 2013 | 20 | 2013 |
| Delay locked loop, electronic device including the same, and method of operating the same HC Kang, KH Ryu, SO Jung, W Lee, DH Lee, A Joo, J Choi US Patent 8,049,543, 2011 | 20 | 2011 |
| Process variation tolerant all-digital multiphase DLL for DDR3 interface HC Kang, KH Ryu, DH Lee, W Lee, SH Kim, JR Choi, SO Jung IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 20 | 2010 |
| A wideband receiver employing PWM-based harmonic rejection downconversion H Kang, WG Ho, V Singh, R Gharpurey 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 364-367, 2017 | 16 | 2017 |
| Low voltage time-based matrix multiplier-and-accumulator for neural computing system S Hong, H Kang, J Kim, K Cho Electronics 9 (12), 2138, 2020 | 10 | 2020 |
| Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs JH Park, H Kang, DH Jung, K Ryu, SO Jung IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 413-421, 2015 | 7 | 2015 |
| A 1.3 v wideband RF-PWM cartesian transmitter employing analog outphasing and a switched-capacitor class-d output stage H Kang, VS Rayudu, KY Kim, R Gharpurey 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 291-294, 2020 | 5 | 2020 |
| Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory H Kang, J Kim, H Jeong, YH Yang, SO Jung IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 752-765, 2015 | 4 | 2015 |
| Clock delay circuit and delay locked loop including the same J Choi, SO Jung, S Kim, H Kang, K Ryu US Patent 8,493,116, 2013 | 4 | 2013 |
| An N-path filter with multiphase PWM clocks for harmonic response suppression VS Rayudu, H Kang, R Gharpurey 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020 | 3 | 2020 |
| A Harmonic Rejection Downconverter with a GHz PWM-Based LO H Kang, R Gharpurey 2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS), 1-3, 2018 | 2 | 2018 |
| A broadband spectrum channelizer with PWM-LO based sub-band equalization KY Kim, H Kang, V Singh, R Gharpurey 2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS), 1-4, 2018 | 2 | 2018 |
| RF pulse-width-modulation generator employing a delay-locked-loop for a wideband transmitter H Kang, VS Rayudu, KY Kim, R Gharpurey 2018 Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), 1-4, 2018 | 2 | 2018 |
| Efficiency Analysis of a Switched-Capacitor Quadrature Power Amplifier Employing RF Pulse-Width-Modulation H Kang, KY Kim, R Gharpurey 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems …, 2020 | | 2020 |
| Wideband receiver and transmitter architectures employing pulse width modulation H Kang | | 2019 |
| Phase-locked loop circuit including voltage down converter consisting of passive element H Kang US Patent 9,467,155, 2016 | | 2016 |
