| 3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance K Monta, H Sonoda, T Okidono, Y Araga, N Watanabe, H Shimamoto, ... IEEE Transactions on Electron Devices 68 (4), 2077-2082, 2021 | 19 | 2021 |
| Multiphysics simulation of EM side-channels from silicon backside with ML-based auto-POI Identification L Lin, D Zhu, J Wen, H Chen, Y Lu, N Chang, C Chow, H Shrivastav, ... 2021 IEEE International Symposium on Hardware Oriented Security and Trust …, 2021 | 15 | 2021 |
| Fast and comprehensive simulation methodology for layout-based power-noise side-channel leakage analysis L Lin, D Selvakumaran, D Zhu, N Chang, C Chow, M Nagata, K Monta 2020 IEEE International Symposium on Smart Electronic Systems (iSES …, 2020 | 11 | 2020 |
| Secure 3D CMOS chip stacks with backside buried metal power delivery networks for distributed decoupling capacitance H Sonoda, K Monta, T Okidono, Y Araga, N Watanabe, H Shimamoto, ... 2020 IEEE International Electron Devices Meeting (IEDM), 31.5. 1-31.5. 4, 2020 | 9 | 2020 |
| Characterization of Backside ESD Impacts on Integrated Circuits T Wadatsumi, K Kawai, R Hasegawa, K Monta, T Miki, M Nagata 2023 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2023 | 3 | 2023 |
| Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis K Monta, L Lin, J Wen, H Shrivastav, C Chow, H Chen, J Geada, ... ACM Journal on Emerging Technologies in Computing Systems 19 (1), 1-23, 2022 | 3 | 2022 |
| Testing embedded toggle pattern generation through on-chip IR drop monitoring K Monta, L Kataselas, F Fodor, A Hatzopoulos, M Nagata, EJ Marinissen 2021 IEEE European Test Symposium (ETS), 1-4, 2021 | 3 | 2021 |
| On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection R Hasegawa, K Monta, T Wadatsumi, T Miki, M Nagata International Workshop on Constructive Side-Channel Analysis and Secure …, 2024 | 2 | 2024 |
| Near Field Measurements of Sub-millimeter-wave Noise Emission from Digital Integrated Circuits K Watanabe, T Wadatsumi, K Monta, M Aoi, M Komatsu, R Sakai, ... 2021 13th International Workshop on the Electromagnetic Compatibility of …, 2022 | 1 | 2022 |
| Chip-Backside Vulnerability to Intentional Electromagnetic Interference in Integrated Circuits T Wadatsumi, K Monta, Y Hayashi, T Miki, AA Hatzopoulos, A Barić, ... IEEE Transactions on Electromagnetic Compatibility, 2024 | | 2024 |
| Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation H Li, L Lin, N Chang, S Chowdhury, D Mcguire, B Novakovic, K Monta, ... 2024 IEEE International Symposium on Hardware Oriented Security and Trust …, 2024 | | 2024 |
| On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits K Monta, M Nagata, J Balasch, I Verbauwhede 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | | 2023 |
| A Si-Interposer with Buried Cu Metal Stripes and Bonded to Si-Substrate Backside for Security IC Chips T Wadatsumi, R Hasegawa, K Monta, T Okidono, T Miki, M Nagata 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), 951-954, 2023 | | 2023 |
| Exploration of hardware Trojan detection through power supply current simulation T Oki, K Monta, T Miki, M Nagata IEICE Technical Report; IEICE Tech. Rep. 123 (6), 1-5, 2023 | | 2023 |
| Exploration of analysis methods of electromagnetic fault injection attacks on cryptographic IC chips Y Hayashi, R Hasegawa, T Wadatsumi, K Monta, T Miki, M Nagata IEICE Technical Report; IEICE Tech. Rep. 123 (6), 11-15, 2023 | | 2023 |
| Electromagnetic fault injection attacks on cryptographic IC chips and analysis of internal voltage fluctuation R Hasegawa, T Wadatsumi, K Monta, T Miki, M Nagata IEICE Technical Report; IEICE Tech. Rep. 123 (6), 16-19, 2023 | | 2023 |
| Side-channel Information Leakage Resistance Evaluation of Cryptographic Multi-chip Modules T Matsumaru, K Monta, T Okidono, T Miki, M Nagata IEICE Technical Report; IEICE Tech. Rep. 122 (403), 273-278, 2023 | | 2023 |
| Side-Channel Leakage Evaluation of 3D CMOS Chip Stacking K MONTA, R HASEGAWA, T MIKI, M NAGATA 電子情報通信学会技術研究報告 (Web) 123 (235 (HWS2023 54-58)), 16-19, 2023 | | 2023 |
| Evaluation of power delivery networks in secure semiconductor systems M Mashiba, K Monta, T Okidono, T Miki, M Nagata IEICE Technical Report; IEICE Tech. Rep. 122 (284), 82-86, 2022 | | 2022 |
| Evaluating system level security of cryptography module T Matsumaru, K Monta, T Okidono, T Miki, M Nagata IEICE Technical Report; IEICE Tech. Rep. 122 (284), 78-81, 2022 | | 2022 |
