| Performance evaluation of domino logic circuits for wide fan-in gates with FinFET AK Dadoria, K Khare, U Panwar, A Jain Microsystem Technologies 24, 3341-3348, 2018 | 14 | 2018 |
| Comparison on different domino logic design for high-performance and leakage-tolerant wide OR gate U Panwar, AK Dadoria International Journal of Engineering Research and Applications 3 (6), 2048-2052, 2013 | 5 | 2013 |
| Integrating flipped drain and power gating techniques for efficient FinFET logic circuits AK Dadoria, K Khare, TK Gupta, U Panwar International Journal of Numerical Modelling: Electronic Networks, Devices …, 2018 | 4 | 2018 |
| A novel technique of leakage power reduction in 9T SRAM design in FinFET technology N Sharma, U Panwar, V Singh 2016 6th International Conference-Cloud System and Big Data Engineering …, 2016 | 4 | 2016 |
| Optimization of low power CMOS based voltage reference generator in 32nm S Meshram, U Panwar IJARCCE 7 (8), 47, 2018 | 3 | 2018 |
| Gate replacement with PMOS stacking for leakage reduction in VLSI circuits U Panwar, K Khare International Journal of Numerical Modelling: Electronic Networks, Devices …, 2016 | 3 | 2016 |
| Gate replacement technique with thick Tox to mitigate leakage with zero delay penalty for DSM CMOS circuit U Panwar, K Khare 2015 International Conference on Industrial Instrumentation and Control …, 2015 | 3 | 2015 |
| Edge-AI in Healthcare: Trends and Future Perspectives S Vyas, A Upadhyaya, D Bhargava, VK Shukla CRC Press, 2023 | 2 | 2023 |
| Design and implementation of ternary adder for High-Performance arithmetic applications by using CNTFET material U Panwar, P Sharma Materials Today: Proceedings 63, 773-777, 2022 | 2 | 2022 |
| A Novel Technique to improve Performance Evaluation of Domino Logic Circuits in CMOS and FinFET Technology U Panwar, A Shrivastava 2nd International Conference on Data, Engineering and Applications (IDEA), 1-5, 2020 | 2 | 2020 |
| Leakage Reduction by Integrating IVC and ALS Technique in 65 nm CMOS One Bit Adder Circuit U Panwar, K Khare Emerging Research in Computing, Information, Communication and Applications …, 2015 | 2 | 2015 |
| An algorithmic approach for leakage current reduction in deep sub-micron CMOS circuits MVP Done, U Panwar, K Khare 2014 International Conference on Advances in Electronics Computers and …, 2014 | 2 | 2014 |
| A novel technique in Adiabatic logic for ultra low power in DSM technology MF Khan, U Panwar 2018 International Conference on Recent Innovations in Electrical …, 2018 | 1 | 2018 |
| High Performance VLSI Architecture for Transpose Form FIR Filter using Integrated Module A Upadhyay, U Panwar 2018 International Conference on Computer Communication and Informatics …, 2018 | 1 | 2018 |
| Comparative Analysis of Existing Clock Gating ALU V Prajapati, U Panwar International journal of scientific and research publication 6 (5), 2016 | 1 | 2016 |
| Variants-based gate modification (VGM) technique for reducing leakage power and short channel effect in DSM circuits U Panwar, AK Dadoria Advanced MOS Devices and their Circuit Applications, 118-130, 2024 | | 2024 |
| Measurement of back-gate biasing for ultra-low-power subthreshold logic in FinFET device AK Dadoria, U Panwar, NK Garg Advanced MOS Devices and their Circuit Applications, 49-55, 2024 | | 2024 |
| A melanoma skin cancer detection and analysis using dermoscopy image processing K Tomar, U Panwar, R Gupta AIP Conference Proceedings 2855 (1), 2023 | | 2023 |
| Transforming healthcare with machine-learning and deep-learning approaches K Tahiliani, U Panwar Edge-AI in Healthcare, 45-60, 2023 | | 2023 |
| A Novel Approach in Power gated Adiabatic Logic for Ultra Low Power Applications R Singh, U Panwar | | 2023 |
Anita JainAssociate Professor, Cummins College of Engg, Pune在 cumminscollege.in 的电子邮件经过验证
Anita JainAssociate Professor, Cummins College of Engg, Pune在 cumminscollege.in 的电子邮件经过验证
tarun guptaAssistant Professor of Electronics and Communication Engineering, MANIT, Bhopal在 manit.ac.in 的电子邮件经过验证