| Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain RC Tekumalla, P Krishnamoorthy, NA Pol, V Sreekumar US Patent 8,726,108, 2014 | 17 | 2014 |
| Integrated circuit having clock gating circuitry responsive to scan shift control signal RC Tekumalla, P Krishnamoorthy US Patent 8,904,255, 2014 | 15 | 2014 |
| Scan test circuitry with delay defect bypass functionality RC Tekumalla, P Krishnamoorthy US Patent 8,645,778, 2014 | 14 | 2014 |
| Low-power and area-efficient scan cell for integrated circuit testing RC Tekumalla, P Kumar, P Krishnamoorthy, P Madhani US Patent 8,566,658, 2013 | 12 | 2013 |
| At-speed scan testing of interface functional logic of an embedded memory or other circuit core RC Tekumalla, P Krishnamoorthy US Patent 8,924,801, 2014 | 8 | 2014 |
| Scan test circuitry configured to prevent capture of potentially non-deterministic values RC Tekumalla, P Krishnamoorthy US Patent 8,700,962, 2014 | 6 | 2014 |
| On-chip clock testing and frequency measurement R Tekumalla, P Krishnamoorthy 2014 IEEE 23rd North Atlantic Test Workshop, 11-14, 2014 | 5 | 2014 |
| Integrated circuit comprising scan test circuitry with parallel reordered scan chains RC Tekumalla, P Krishnamoorthy, P Madhani US Patent 8,793,546, 2014 | 4 | 2014 |
| Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testing RC Tekumalla, P Krishnamoorthy US Patent 8,677,200, 2014 | 3 | 2014 |
| Quotient prediction for low power division P Krishnamoorthy, R Tekumalla 2013 IEEE International SOC Conference, 273-277, 2013 | 3 | 2013 |
| An attempt to completely utilize the bandwidth capability of PCI-X 133 MHz devices in a 66 MHz PCI-X local bus K Prakash Proceedings Fourth International Conference/Exhibition on High Performance …, 2000 | 3 | 2000 |
| Local repair signature handling for repairable memories R Tekumalla, P Krishnamoorthy 2014 IEEE 23rd North Atlantic test workshop, 1-5, 2014 | 2 | 2014 |
| Divider circuitry with quotient prediction based on estimated partial remainder P Krishnamoorthy, RC Tekumalla US Patent App. 13/296,754, 2013 | 2 | 2013 |
| Instruction address encoding and decoding based on program construct groups P Krishnamoorthy, RC Tekumalla, P Madhani US Patent 9,348,593, 2016 | 1 | 2016 |
| Local Repair Signature Handling for Repairable Memories RC Tekumalla, P Krishnamoorthy US Patent App. 13/859,507, 2014 | 1 | 2014 |
| Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry RC Tekumalla, P Kumar, P Krishnamoorthy US Patent App. 13/743,687, 2014 | 1 | 2014 |
| Coding circuitry for difference-based data transformation P Krishnamoorthy, RC Tekumalla, P Madhani US Patent 8,711,013, 2014 | 1 | 2014 |
| Clock control for reducing timing exceptions in scan testing of an integrated circuit RC Tekumalla, P Krishnamoorthy, V Sharma US Patent 8,799,731, 2014 | | 2014 |
| Power aware transformation of bandlimited signals P Krishnamoorthy, R Tekumalla 2013 IEEE International SOC Conference, 178-183, 2013 | | 2013 |
| NATW 2014 R Tekumalla, P Krishnamoorthy | | |
