| Low power domino logic circuits in deep-submicron technology using CMOS S Garg, TK Gupta Engineering Science and Technology, an International Journal 21 (4), 625-638, 2018 | 60 | 2018 |
| Lector with footed-diode inverter: A technique for leakage reduction in domino circuits TK Gupta, K Khare Circuits, Systems, and Signal Processing 32, 2707-2722, 2013 | 42 | 2013 |
| Reliable high-yield CNTFET-based 9T SRAM operating near threshold voltage region PK Patel, MM Malik, TK Gupta Journal of Computational Electronics 17, 774-783, 2018 | 32 | 2018 |
| FDSTDL: Low‐power technique for FinFET domino circuits S Garg, TK Gupta International Journal of circuit Theory and applications 47 (6), 917-940, 2019 | 26 | 2019 |
| Design of high-speed low variation static noise margin ternary S-RAM cells Y Shrivastava, TK Gupta IEEE Transactions on Device and Materials Reliability 21 (1), 102-110, 2021 | 25 | 2021 |
| Ultra-low power FinFET-based domino circuits AK Dadoria, K Khare, TK Gupta, RP Singh International Journal of Electronics 104 (6), 952-967, 2017 | 25 | 2017 |
| Analysis and design of lector-based dual-Vt domino logic with reduced leakage current TK Gupta, AK Pandey, OP Meena Circuit World 43 (3), 97-104, 2017 | 20 | 2017 |
| Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM PK Patel, MM Malik, TK Gupta Microelectronics Journal 90, 19-28, 2019 | 17 | 2019 |
| Ultra low power adiabatic logic using diode connected DC biased PFAL logic A Agrawal, TK Gupta, AK Dadoria Advances in Electrical and Electronic Engineering 15 (1), 46-54, 2017 | 16 | 2017 |
| A novel high-performance lekage-tolerant, wide fan-in domino logic circuit in deep-submicron technology A Dadoria, K Khare, TK Gupta, RP Singh Circuits and Systems 6 (04), 103, 2015 | 15 | 2015 |
| A 4: 1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology S Garg, TK Gupta, AK Pandey International Journal of Electronics 107 (4), 513-541, 2020 | 14 | 2020 |
| Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques PK Patel, M Malik, TK Gupta International Journal of Numerical Modelling: Electronic Networks, Devices …, 2019 | 14 | 2019 |
| Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits AK Dadoria, K Khare, TK Gupta, N Khare Journal of Computational Electronics 16, 867-874, 2017 | 14 | 2017 |
| A new technique for designing low-power high-speed domino logic circuits in FinFET technology S Garg, TK Gupta Journal of Circuits, Systems and Computers 28 (10), 1950165, 2019 | 13 | 2019 |
| Low leakage domino logic circuit for wide fan‐in gates using CNTFET S Garg, TK Gupta IET Circuits, Devices & Systems 13 (2), 163-173, 2019 | 13 | 2019 |
| Design of low‐power high‐speed CNFET 1‐trit unbalanced ternary multiplier Y Shrivastava, TK Gupta International Journal of Numerical Modelling: Electronic Networks, Devices …, 2020 | 12 | 2020 |
| A novel efficient adiabatic logic design for ultra low power A Agrawal, TK Gupta, AK Dadoria, D Kumar 2016 International Conference on ICT in Business Industry & Government …, 2016 | 12 | 2016 |
| Design of compact reliable energy efficient read disturb free 17T CNFET Ternary S-RAM cell Y Shrivastava, TK Gupta IEEE Transactions on Device and Materials Reliability 21 (4), 508-517, 2021 | 11 | 2021 |
| Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs A Kumar, TK Gupta, BP Shrivastava, A Gupta Microelectronics Journal 134, 105720, 2023 | 10 | 2023 |
| Very low power domino logic circuits using carbon nanotube field effect transistor technology S Garg, TK Gupta Journal of Nanoelectronics and Optoelectronics 14 (1), 19-32, 2019 | 10 | 2019 |
