| Low latency YOLOv3-tiny accelerator for low-cost FPGA using general matrix multiplication principle T Adiono, A Putra, N Sutisna, I Syafalni, R Mulyawan IEEE access 9, 141890-141913, 2021 | 31 | 2021 |
| Strix: An end-to-end streaming architecture with two-level ciphertext batching for fully homomorphic encryption with programmable bootstrapping A Putra, Prasetiyo, Y Chen, J Kim, JY Kim Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 10 | 2023 |
| Data acquisition software for wheel drive electronics automated measurement system A Putra, R Darmakusuma, H Septanto AIP Conference Proceedings 2366 (1), 2021 | 2 | 2021 |
| Hardware dataflow for convolutional neural network accelerator A Putra, T Adiono, N Sutisna, I Syafalni, R Mulyawan 2021 International Symposium on Electronics and Smart Devices (ISESD), 1-6, 2021 | 2 | 2021 |
| Full Custom Layout of Neural Network Processing Element Using Push Pull D Flip Flop and Modified Carry Look Ahead Adder A Putra, T Adiono 2021 International Symposium on Electronics and Smart Devices (ISESD), 1-6, 2021 | 1 | 2021 |
| Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse A Putra, JY Kim 2024 IEEE International Symposium on High-Performance Computer Architecture …, 2024 | | 2024 |
Trio AdionoProfessor in Chip Design, STEI, Institut Teknologi Bandung在 stei.itb.ac.id 的电子邮件经过验证
