| Wavelet based fault detection in analog VLSI circuits using neural networks P Kalpana, K Gunavathi Applied Soft Computing 8 (4), 1592-1598, 2008 | 31 | 2008 |
| Novel reversible design of advanced encryption standard cryptographic algorithm for wireless sensor networks P Saravanan, P Kalpana Wireless Personal Communications 100, 1427-1458, 2018 | 23 | 2018 |
| A novel and systematic approach to implement reversible gates in quantum dot cellular automata P Saravanan, P Kalpana Quantum 2 (5), 15, 2013 | 20 | 2013 |
| A novel specification based test pattern generation using genetic algorithm and wavelets P Kalpana, K Gunavathi 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 17 | 2005 |
| Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks P Kalpana, K Gunavathi ETRI journal 31 (2), 209-214, 2009 | 16 | 2009 |
| A novel implicit parametric fault detection method for analog/mixed signal circuits using wavelets P Kalpana, K Gunavathi ICGST-PDCS Journal 7 (1), 43-48, 2007 | 14 | 2007 |
| Security aspects of SIP based VoIP networks: A survey V Srihari, P Kalpana, R Anitha Second International Conference on Current Trends In Engineering and …, 2014 | 13 | 2014 |
| Fault oriented Test Pattern Generator for Digital to Analog converters P Kalpana, K Gunavathi Academic Open Internet Journal 13, 2004 | 12 | 2004 |
| An intelligent AODV routing with energy efficient weight based clustering algorithm (EEWCA) in wireless Ad hoc network (WANET) S Tamizharasu, P Kalpana Wireless Networks 29 (6), 2703-2716, 2023 | 10 | 2023 |
| Power analysis attack using neural networks with wavelet transform as pre-processor P Saravanan, P Kalpana, V Preethisri, V Sneha 18th International Symposium on VLSI Design and Test, 1-6, 2014 | 10 | 2014 |
| An energy efficient XOR gate implementation resistant to power analysis attacks P Saravanan, P Kalpana J. Eng. Sci. Technol 10 (1), 1275-1292, 2015 | 9 | 2015 |
| A novel approach to attack smartcards using machine learning method P Saravanan, P Kalpana NISCAIR-CSIR, India, 2017 | 8 | 2017 |
| Power analysis attack on 8051 microcontrollers P Saravanan, N Rajadurai, P Kalpana 2014 IEEE International Conference on Computational Intelligence and …, 2014 | 8 | 2014 |
| Design and implementation of efficient vedic multiplier using reversible logic P Saravanan, P Chandrasekar, L Chandran, N Sriram, P Kalpana Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 8 | 2012 |
| Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography P Saravanan, P Kalpana Journal of Circuits, Systems and Computers 24 (08), 1550122, 2015 | 7 | 2015 |
| Energy efficient reversible building blocks resistant to power analysis attacks P Saravanan, P Kalpana Journal of Circuits, Systems and Computers 23 (09), 1450127, 2014 | 6 | 2014 |
| A high-throughput ASIC implementation of configurable advanced encryption standard (AES) processor P Saravanan, NR Devi, G Swathi, DP Kalpana IJCA Special Issue on Network Security and Cryptography, NSC, 1-6, 2011 | 6 | 2011 |
| Recycled integrated circuit detection using reliability analysis and machine learning algorithms US Santhana Krishnan, K Palanisamy IET Computers & Digital Techniques 15 (1), 20-35, 2021 | 4 | 2021 |
| Behavioral modeling and fault simulation of system on chips P Kalpana, K Gunavathi Academic Open Internet Journal 13, 1-6, 2004 | 4 | 2004 |
| Reliability and Circuit Timing Analysis with HCI and NBTI S Udaya Shankar, P Kalpana Advances in VLSI, Communication, and Signal Processing: Select Proceedings …, 2021 | 3 | 2021 |
