| The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ... IEEE Micro 38 (2), 30-41, 2018 | 122 | 2018 |
| A modular digital VLSI flow for high-productivity SoC design B Khailany, E Khmer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 75 | 2018 |
| Enabling realistic fine-grain voltage scaling with reconfigurable power distribution networks W Godycki, C Torng, I Bukreyev, A Apsel, C Batten 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 381-393, 2014 | 64 | 2014 |
| Ultra-elastic cgras for irregular loop specialization C Torng, P Pan, Y Ou, C Tan, C Batten 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 44 | 2021 |
| Microarchitectural mechanisms to exploit value structure in SIMT architectures J Kim, C Torng, S Srinath, D Lockhart, C Batten Proceedings of the 40th Annual International Symposium on Computer …, 2013 | 44 | 2013 |
| Celerity: An open source RISC-V tiered accelerator fabric T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ... Symp. on High Performance Chips (Hot Chips), 2017 | 36 | 2017 |
| Asymmetry-aware work-stealing runtimes C Torng, M Wang, C Batten ACM SIGARCH Computer Architecture News 44 (3), 40-52, 2016 | 36 | 2016 |
| Creating an agile hardware design flow R Bahr, C Barrett, N Bhagdikar, A Carsello, R Daly, C Donovick, D Durst, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 30 | 2020 |
| A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... 2019 Symposium on VLSI Circuits, C30-C31, 2019 | 29 | 2019 |
| Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019 | 28 | 2019 |
| Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a coarse-grained reconfigurable array for flexible acceleration of dense linear algebra A Carsello, K Feng, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 19 | 2022 |
| PyOCN: A unified framework for modeling, testing, and evaluating on-chip networks C Tan, Y Ou, S Jiang, P Pan, C Torng, S Agwa, C Batten 2019 IEEE 37th International Conference on Computer Design (ICCD), 437-445, 2019 | 19 | 2019 |
| Aha: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers K Koul, J Melchert, K Sreedhar, L Truong, G Nyengele, K Zhang, Q Liu, ... ACM Transactions on Embedded Computing Systems 22 (2), 1-34, 2023 | 18 | 2023 |
| Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs J Kim, S Jiang, C Torng, M Wang, S Srinath, B Ilbeyi, K Al-Hawaj, C Batten Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 14 | 2017 |
| Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ... 1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017 | 14 | 2017 |
| An open-source python-based hardware generation, simulation, and verification framework SJCTC Batten Workshop on Open-Source EDA Technology (WOSET), 1-5, 2018 | 12 | 2018 |
| Four monolithically integrated switched-capacitor DC–DC converters with dynamic capacitance sharing in 65-nm CMOS I Bukreyev, C Torng, W Godycki, C Batten, A Apsel IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 2035-2047, 2017 | 12 | 2017 |
| A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion K Sreedhar, M Horowitz, C Torng IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022 | 7 | 2022 |
| Canal: A flexible interconnect generator for coarse-grained reconfigurable arrays J Melchert, K Zhang, Y Mei, M Horowitz, C Torng, P Raina IEEE Computer Architecture Letters 22 (1), 45-48, 2023 | 4 | 2023 |
| mflowgen: A modular flow generator and ecosystem for community-driven physical design A Carsello, J Thomas, A Nayak, PH Chen, M Horowitz, P Raina, C Torng Proceedings of the 59th ACM/IEEE Design Automation Conference, 1339-1342, 2022 | 4 | 2022 |
