| A 172 W Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data VR Pamula, JM Valero-Sarmiento, L Yan, A Bozkurt, C Van Hoof, ... IEEE transactions on biomedical circuits and systems 11 (3), 487-496, 2017 | 68 | 2017 |
| 22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data PV Rajesh, JM Valero-Sarmiento, L Yan, A Bozkurt, C Van Hoof, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 386-387, 2016 | 60 | 2016 |
| A single-chip bidirectional neural interface with high-voltage stimulation and adaptive artifact cancellation in standard CMOS JP Uehlin, WA Smith, VR Pamula, EP Pepin, S Perlmutter, V Sathe, ... IEEE Journal of Solid-State Circuits 55 (7), 1749-1761, 2020 | 55 | 2020 |
| A 680 nA ECG acquisition IC for leadless pacemaker applications L Yan, P Harpe, VR Pamula, M Osawa, Y Harada, K Tamiya, C Van Hoof, ... IEEE transactions on biomedical circuits and systems 8 (6), 779-786, 2014 | 55 | 2014 |
| A 0.0023 mm/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression JP Uehlin, WA Smith, VR Pamula, SI Perlmutter, JC Rudell, VS Sathe IEEE transactions on biomedical circuits and systems 14 (2), 319-331, 2019 | 42 | 2019 |
| Architecture considerations for stochastic computing accelerators VT Lee, A Alaghi, R Pamula, VS Sathe, L Ceze, M Oskin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 39 | 2018 |
| An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS VR Pamula, X Sun, S Kim, F ur Rahman, B Zhang, VS Sathe 2018 IEEE Symposium on VLSI Circuits, 1-2, 2018 | 35 | 2018 |
| 14.5 A 0.6-to-1.1 V computationally regulated digital LDO with 2.79-cycle mean settling time and autonomous runtime gain tracking in 65nm CMOS X Sun, A Boora, W Zhang, VR Pamula, V Sathe 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 230-232, 2019 | 31 | 2019 |
| A unified clock and switched-capacitor-based power delivery architecture for variation tolerance in low-voltage SoC domains F ur Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ... IEEE Journal of Solid-State Circuits 54 (4), 1173-1184, 2019 | 26 | 2019 |
| A novel feature extraction algorithm for on the sensor node processing of compressive sampled photoplethysmography signals VR Pamula, M Verhelst, C Van Hoof, RF Yazicioglu 2015 IEEE SENSORS, 1-4, 2015 | 21 | 2015 |
| Computationally-efficient compressive sampling for low-power pulseoximeter system VR Pamula, M Verhelst, C Van Hoof, RF Yazicioglu 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings, 69-72, 2014 | 21 | 2014 |
| A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit highly digital true-random-number generator with integrated de-correlation and bias correction VR Pamula, X Sun, SM Kim, F ur Rahman, B Zhang, VS Sathe IEEE Solid-State Circuits Letters 1 (12), 237-240, 2018 | 17 | 2018 |
| A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0 V cortex-M0 processor X Sun, S Kim, F ur Rahman, VR Pamula, X Li, N John, VS Sathe 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 302-304, 2018 | 15 | 2018 |
| An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor X Sun, F ur Rahman, VR Pamula, S Kim, X Li, N John, VS Sathe IEEE Journal of Solid-State Circuits 54 (11), 3215-3225, 2019 | 14 | 2019 |
| An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM cortex M0 processor FU Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ... 2018 IEEE Symposium on VLSI Circuits, 65-66, 2018 | 13 | 2018 |
| 19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58 V Microprocessor in 65nm CMOS F ur Rahman, R Pamula, A Boora, X Sun, V Sathe 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 312-314, 2019 | 12 | 2019 |
| A wearable wrist-band with compressive sensing based ultra-low power photoplethysmography readout circuit P Ahmmed, J Dieffenderfer, JM Valero-Sarmiento, VR Pamula, ... 2019 IEEE 16th international conference on wearable and implantable body …, 2019 | 11 | 2019 |
| A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. CH Huang, X Sun, Y Chen, R Pamula, A Mandal, V Sathe ISSCC, 416-418, 2021 | 9 | 2021 |
| A bidirectional brain computer interface with 64-channel recording, resonant stimulation and artifact suppression in standard 65nm cmos J Uehlin, WA Smith, VR Pamula, S Perlmutter, V Sathe, JC Rudell ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 77-80, 2019 | 8 | 2019 |
| Vacuum generating device HY Cho US Patent 6,729,851, 2004 | 7* | 2004 |
