| Parametric analysis of a hybrid 1-bit full adder in UDSM and CNTFET technology NK Niranjan, RB Singh, NZ Rizvi 2016 International Conference on Electrical, Electronics, and Optimization …, 2016 | 8 | 2016 |
| Design and simulation of P-TFET for improved ION/IOFF ratio and subthreshold slope using strained Si1−xGex channel heterojunction S Choudhury, NK Niranjan, KL Baishnab, K Guha Microsystem Technologies 26 (6), 1777-1782, 2020 | 6 | 2020 |
| Modeling and simulation of 2-D SixGe (1-x) source dual-gate pocket NTFET NK Niranjan, P Sarkar, B Bhowmick, M Choudhury, KL Baishnab Micro and Nanostructures 167, 207237, 2022 | 4 | 2022 |
| Effect of metal work function of asymmetric dielectric tunnel FET on its performance NK Niranjan, S Choudhury, M Choudhury, KL Baishnab, K Guha, ... Microsystem Technologies 27, 3757-3762, 2021 | 3 | 2021 |
| Comparative Study on the Role of Different Precursor Salts on Structural, Morphological, and Optoelectronic Characteristics of CH3NH3PbCl3 Perovskite Semiconductor: An … P Sarkar, NK Niranjan, A Srivastava, SK Tripathy, KL Baishnab, ... Journal of Electronic Materials 51 (12), 7105-7112, 2022 | 2 | 2022 |
| 2-D Si0. 8Ge0. 2 source double-gate pocket PTFET for low power application: Modeling and simulation NK Niranjan, P Sarkar, B Bhowmick, M Choudhury, KL Baishnab, SD Lala, ... Materials Science and Engineering: B 303, 117290, 2024 | | 2024 |
| Optimization of 2D Ge-Pocket Asymmetric Dual-Gate Tunnel FETs NK Niranjan, S Choudhary, M Choudhary, KL Baishanb Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings …, 2022 | | 2022 |
| A meta-heuristic algorithm-based optimization δp⁺ Si-Ge gate–drain under-lap n-TFET S Choudhury, NK Neeranjan, KL Baishnab, K Guha 2021 IEEE 18th India Council International Conference (INDICON), 1-5, 2021 | | 2021 |
