| Improved retention time in twin gate 1T DRAM with tunneling based read mechanism N Navlakha, JT Lin, A Kranti IEEE Electron Device Letters 37 (9), 1127-1130, 2016 | 52 | 2016 |
| Retention and scalability perspective of sub-100-nm double gate tunnel FET DRAM N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 64 (4), 1561-1567, 2017 | 40 | 2017 |
| Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering N Navlakha, JT Lin, A Kranti Journal of Applied Physics 119 (21), 2016 | 38 | 2016 |
| Double-gate junctionless 1T DRAM with physical barriers for retention improvement MHR Ansari, N Navlakha, JY Lee, S Cho IEEE Transactions on Electron Devices 67 (4), 1471-1479, 2020 | 33 | 2020 |
| Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM MHR Ansari, N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 65 (3), 1205-1210, 2018 | 32 | 2018 |
| 1T-DRAM with shell-doped architecture MHR Ansari, N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 66 (1), 428-435, 2018 | 25 | 2018 |
| Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability N Navlakha, A Kranti Nanotechnology 28 (44), 445203, 2017 | 14 | 2017 |
| High Retention With-Oxide-Junctionless Architecture for 1T DRAM MHR Ansari, N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 65 (7), 2797-2803, 2018 | 12 | 2018 |
| Raised body doping-less 1T-DRAM with source/drain Schottky contact JT Lin, WT Sun, HH Lin, YJ Chen, N Navlakha, A Kranti IEEE Journal of the Electron Devices Society 7, 276-281, 2019 | 10 | 2019 |
| Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application N Navlakha, A Kranti Journal of Applied Physics 122 (4), 2017 | 8 | 2017 |
| Monte Carlo Study of Si, Ge, and In0.53Ga0.47As n-Channel FinFET Scaling: Channel Orientation, Quantum Confinement, Doping, and Contacts AA Bhatti, N Navlakha, DM Crum, SK Banerjee, LF Register IEEE Nanotechnology Magazine 14 (6), 17-31, 2020 | 4 | 2020 |
| Performance assessment of TFET architectures as 1T-DRAM N Navlakha, MHR Ansari, JT Lin, A Kranti 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 4 | 2018 |
| Band Alignment in Black Phosphorus/Transition Metal Dichalcogenide Heterolayers: Impact of Charge Redistribution, Electric Field, Strain, and Layer Engineering N Navlakha, P Jadaun, LF Register, S Banerjee Journal of Electronic Materials 52, 1474-1483, 2023 | 3 | 2023 |
| Improving charge retention in capacitorless DRAM through material and device innovation MHR Ansari, N Navlakha, JT Lin, A Kranti Japanese Journal of Applied Physics 58 (SB), SBBB03, 2019 | 2 | 2019 |
| Optimization of back gate workfunction, alignment and bias for charge retention in TFET based DRAM N Navlakha, A Kranti, JT Lin 2016 3rd International Conference on Emerging Electronics (ICEE), 1-4, 2016 | 2 | 2016 |
| Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications MH Raza Ansari, N Navlakha, N El-Atab ACS Applied Electronic Materials 5 (12), 7079-7086, 2023 | 1 | 2023 |
| Semi-classical Monte Carlo study of the impact of tensile strain on the performance limits of monolayer MoS2 n-channel MOSFETs AA Bhatti, BT Archer, N Navlakha, LF Register, SK Banerjee Journal of Applied Physics 134 (20), 2023 | 1 | 2023 |
| Architecture evaluation for standalone and embedded 1T-DRAM MHR Ansari, N Navlakha, JT Lin, A Kranti 2019 International Symposium on VLSI Technology, Systems and Application …, 2019 | 1 | 2019 |
| Twin gate tunnel FET based capacitorless dynamic memory N Navlakha, JT Lin, A Kranti 2017 International Symposium on VLSI Technology, Systems and Application …, 2017 | 1 | 2017 |
| Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals N Navlakha, L Garg, D Boolchandani, V Sahula VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India …, 2013 | 1 | 2013 |
