| Device and circuit performance estimation of junctionless bulk FinFETs MH Han, CY Chang, HB Chen, YC Cheng, YC Wu IEEE transactions on electron devices 60 (6), 1807-1813, 2013 | 94 | 2013 |
| Performance comparison between bulk and SOI junctionless transistors MH Han, CY Chang, HB Chen, JJ Wu, YC Cheng, YC Wu IEEE electron device letters 34 (2), 169-171, 2013 | 89 | 2013 |
| A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory SC Chen, TC Chang, PT Liu, YC Wu, PS Lin, BH Tseng, JH Shy, SM Sze, ... IEEE Electron Device Letters 28 (9), 809-811, 2007 | 74 | 2007 |
| A point mutation in the glutamate‐gated chloride channel of Plutella xylostella is associated with resistance to abamectin X Wang, R Wang, Y Yang, S Wu, AO O'Reilly, Y Wu Insect molecular biology 25 (2), 116-125, 2016 | 69 | 2016 |
| Performance of inversion, accumulation, and junctionless mode n-type and p-type bulk silicon FinFETs with 3-nm gate length V Thirunavukkarasu, YR Jhan, YB Liu, YC Wu IEEE electron device letters 36 (7), 645-647, 2015 | 67 | 2015 |
| High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure YC Wu, TC Chang, CY Chang, CS Chen, CH Tu, PT Liu, HW Zan, YH Tai Applied physics letters 84 (19), 3822-3824, 2004 | 60 | 2004 |
| High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory MF Hung, YC Wu, ZY Tang Applied Physics Letters 98 (16), 2011 | 54 | 2011 |
| 3D TCAD simulation for CMOS nanoeletronic devices YC Wu, YR Jhan Springer, 2018 | 48 | 2018 |
| Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope HB Chen, YC Wu, CY Chang, MH Han, NH Lu, YC Cheng 2013 Symposium on VLSI Technology, T232-T233, 2013 | 47 | 2013 |
| Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels SC Chen, TC Chang, PT Liu, YC Wu, PH Yeh, CF Weng, SM Sze, ... Applied physics letters 90 (12), 2007 | 47 | 2007 |
| Performance evaluation of silicon and germanium ultrathin body (1 nm) junctionless field-effect transistor with ultrashort gate length (1 nm and 3 nm) YR Jhan, V Thirunavukkarasu, CP Wang, YC Wu IEEE Electron Device Letters 36 (7), 654-656, 2015 | 42 | 2015 |
| Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis MH Han, CY Chang, YR Jhan, JJ Wu, HB Chen, YC Cheng, YC Wu IEEE electron device letters 34 (2), 157-159, 2013 | 40 | 2013 |
| Twin thin-film transistor nonvolatile memory with an indium–gallium–zinc–oxide floating gate MF Hung, YC Wu, JJ Chang, KS Chang-Liao IEEE Electron Device Letters 34 (1), 75-77, 2012 | 40 | 2012 |
| Introduction of synopsys sentaurus TCAD simulation YC Wu, YR Jhan, YC Wu, YR Jhan 3D TCAD Simulation for CMOS Nanoeletronic Devices, 1-17, 2018 | 39 | 2018 |
| Analysis of Ge-Si heterojunction nanowire tunnel FET: impact of tunneling window of band-to-band tunneling model ED Kurniawan, SY Yang, V Thirunavukkarasu, YC Wu Journal of The Electrochemical Society 164 (11), E3354, 2017 | 36 | 2017 |
| High speed and large memory window ferroelectric HfZrO₂ FinFET for high-density nonvolatile memory SC Yan, GM Lan, CJ Sun, YH Chen, CH Wu, HK Peng, YH Lin, YH Wu, ... IEEE Electron Device Letters 42 (9), 1307-1310, 2021 | 35 | 2021 |
| Characteristics of gate-all-around junctionless poly-Si TFTs with an ultrathin channel HB Chen, CY Chang, NH Lu, JJ Wu, MH Han, YC Cheng, YC Wu IEEE electron device letters 34 (7), 897-899, 2013 | 35 | 2013 |
| Optimization of CFETR CSMC cabling based on numerical modeling and experiments J Qin, C Dai, B Liu, Y Wu, F Liu, G Liao, T Xue, Z Wei, A Nijhuis, C Zhou, ... Superconductor Science and Technology 28 (12), 125008, 2015 | 34 | 2015 |
| Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels YC Wu, TC Chang, PT Liu, CS Chen, CH Tu, HW Zan, YH Tai, CY Chang IEEE transactions on electron devices 52 (10), 2343-2346, 2005 | 33 | 2005 |
| Characterizing the electrical properties of a novel junctionless poly-Si ultrathin-body field-effect transistor using a trench structure MS Yeh, YC Wu, MH Wu, MH Chung, YR Jhan, MF Hung IEEE Electron Device Letters 36 (2), 150-152, 2014 | 32 | 2014 |
