| Digital integrated circuits JM Rabaey, A Chandrakasan, B Nikolic Prentice hall, 2002 | 9867 | 2002 |
| Introduction to stochastic processes in biostatistics CL Chiang (No Title), 1968 | 2710* | 1968 |
| Improved sense-amplifier-based flip-flop: Design and measurements B Nikolic, VG Oklobdzija, V Stojanovic, W Jia, JKS Chiu, MMT Leung IEEE Journal of Solid-State Circuits 35 (6), 876-884, 2000 | 608 | 2000 |
| A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR Y Chiu, PR Gray, B Nikolic IEEE Journal of Solid-State Circuits 39 (12), 2139-2151, 2004 | 381 | 2004 |
| FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 295 | 2018 |
| Least mean square adaptive digital background calibration of pipelined analog-to-digital converters Y Chiu, CW Tsang, B Nikolic, PR Gray IEEE Transactions on Circuits and Systems I: Regular Papers 51 (1), 38-46, 2004 | 278 | 2004 |
| A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS D Stepanovic, B Nikolic IEEE Journal of Solid-State Circuits 48 (4), 971-982, 2013 | 272 | 2013 |
| Methods for true energy-performance optimization D Markovic, V Stojanovic, B Nikolic, MA Horowitz, RW Brodersen IEEE Journal of Solid-State Circuits 39 (8), 1282-1293, 2004 | 262 | 2004 |
| Clocked CMOS adiabatic logic with integrated single-phase power-clock supply D Maksimovic, VG Oklobdzija, B Nikolic, KW Current IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 460-463, 2000 | 251 | 2000 |
| Level conversion for dual-supply systems F Ishihara, F Sheikh, B Nikolić Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 245 | 2003 |
| Chipyard: Integrated design, simulation, and implementation framework for custom socs A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... IEEE Micro 40 (4), 10-21, 2020 | 242 | 2020 |
| An efficient 10GBASE-T ethernet LDPC decoder design with low error floors Z Zhang, V Anantharam, MJ Wainwright, B Nikolic IEEE Journal of Solid-State Circuits 45 (4), 843-855, 2010 | 239 | 2010 |
| Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes L Dolecek, Z Zhang, V Anantharam, MJ Wainwright, B Nikolic IEEE Transactions on Information Theory 56 (1), 181-201, 2009 | 232 | 2009 |
| FinFET-based SRAM design Z Guo, S Balasubramanian, R Zlatanovici, TJ King, B Nikolić Proceedings of the 2005 international symposium on Low power electronics and …, 2005 | 223 | 2005 |
| Analysis and design of low-energy flip-flops D Markovic, B Nikolic, R Brodersen Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 217 | 2001 |
| High throughput low-density parity-check decoder architectures E Yeo, P Pakzad, B Nikolic, V Anantharam GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No. 01CH37270 …, 2001 | 212 | 2001 |
| Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration H Genc, S Kim, A Amid, A Haj-Ali, V Iyer, P Prakash, J Zhao, D Grubb, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 769-774, 2021 | 192 | 2021 |
| Large-scale SRAM variability characterization in 45 nm CMOS Z Guo, A Carlson, LT Pang, KT Duong, TJK Liu, B Nikolic IEEE Journal of Solid-State Circuits 44 (11), 3174-3192, 2009 | 185 | 2009 |
| Design of energy-and cost-efficient massive MIMO arrays A Puglielli, A Townley, G LaCaille, V Milovanović, P Lu, K Trotskovsky, ... Proceedings of the IEEE 104 (3), 586-606, 2015 | 182 | 2015 |
| A design environment for high-throughput low-power dedicated signal processing systems WR Davis, N Zhang, K Camera, D Markovic, T Smilkstein, MJ Ammer, ... IEEE Journal of Solid-State Circuits 37 (3), 420-431, 2002 | 166 | 2002 |
Jan RabaeyProfessor of EECS, University of California at Berkeley在 berkeley.edu 的电子邮件经过验证
