Improving the performance of OpenCL-based FPGA accelerator for convolutional neural network J Zhang, J Li Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 271 | 2017 |
1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing J Li, R Montoye, M Ishii, K Stawiasz, T Nishida, K Maloney, G Ditlow, ... VLSI Circuits (VLSIC), 2013 Symposium on, C104-C105, 2013 | 243 | 2013 |
Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective J Li, P Ndai, A Goel, S Salahuddin, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (12 …, 2009 | 171 | 2009 |
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement J Li, C Augustine, S Salahuddin, K Roy Proceedings of the 45th annual Design Automation Conference, 278-283, 2008 | 105 | 2008 |
Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells Q Luo, X Xu, H Liu, H Lv, T Gong, S Long, Q Liu, H Sun, W Banerjee, L Li, ... 2015 IEEE International Electron Devices Meeting (IEDM), 10.2. 1-10.2. 4, 2015 | 99 | 2015 |
Virtualizing FPGAs in the cloud Y Zha, J Li Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 87 | 2020 |
Boosting the performance of FPGA-based graph processor using hybrid memory cube: A case for breadth first search J Zhang, S Khoram, J Li Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 84 | 2017 |
Adaptive quantization of neural networks S Khoram, J Li International Conference on Learning Representations, 2018 | 69 | 2018 |
Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling X Xu, Q Luo, T Gong, H Lv, S Long, Q Liu, SS Chung, J Li, M Liu 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 63 | 2016 |
A case for small row buffers in non-volatile main memories J Meza, J Li, O Mutlu 2012 IEEE 30th International Conference on Computer Design (ICCD), 484-485, 2012 | 62 | 2012 |
Variable-latency adder (VL-adder) designs for low power and NBTI tolerance Y Chen, H Li, CK Koh, G Sun, J Li, Y Xie, K Roy IEEE transactions on very large scale integration (VLSI) systems 18 (11 …, 2009 | 62 | 2009 |
Resistance drift in phase change memory J Li, B Luan, C Lam 2012 IEEE International Reliability Physics Symposium (IRPS), 6C. 1.1-6C. 1.6, 2012 | 61 | 2012 |
Reconfigurable multi-level sensing scheme for semiconductor memories CH Lam, SC Lewis, J Li US Patent 8,717,802, 2014 | 60 | 2014 |
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement J Li, H Liu, S Salahuddin, K Roy 2008 IEEE Custom Integrated Circuits Conference, 193-196, 2008 | 59 | 2008 |
A low power phase change memory using thermally confined TaN/TiN bottom electrode JY Wu, M Breitwisch, S Kim, TH Hsu, R Cheek, PY Du, J Li, EK Lai, Y Zhu, ... 2011 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2011 | 58 | 2011 |
Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability X Zhang, J Li, M Grubbs, M Deal, B Magyari-Kope, BM Clemens, Y Nishi 2009 IEEE International Electron Devices Meeting (IEDM), 57-60, 2009 | 58 | 2009 |
Degree-aware hybrid graph traversal on FPGA-HMC platform J Zhang, J Li Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 54 | 2018 |
Challenges and opportunities: From near-memory computing to in-memory computing S Khoram, Y Zha, J Zhang, J Li Proceedings of the 2017 ACM on International Symposium on Physical Design, 43-46, 2017 | 50 | 2017 |
Accelerating graph analytics by co-optimizing storage and access on an FPGA-HMC platform S Khoram, J Zhang, M Strange, J Li Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 49 | 2018 |
Variable-latency adder (VL-adder) new arithmetic circuit design practice to overcome NBTI Y Chen, H Li, J Li, CK Koh Proceedings of the 2007 international symposium on Low power electronics and …, 2007 | 47 | 2007 |