| An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS VR Pamula, X Sun, S Kim, F ur Rahman, B Zhang, VS Sathe 2018 IEEE Symposium on VLSI Circuits, 1-2, 2018 | 34 | 2018 |
| A unified clock and switched-capacitor-based power delivery architecture for variation tolerance in low-voltage SoC domains F ur Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ... IEEE Journal of Solid-State Circuits 54 (4), 1173-1184, 2019 | 26 | 2019 |
| A 1–2 GHz computational-locking ADPLL with sub-20-cycle locktime across PVT variation F ur Rahman, G Taylor, V Sathe IEEE Journal of Solid-State Circuits 54 (9), 2487-2500, 2019 | 21 | 2019 |
| A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit highly digital true-random-number generator with integrated de-correlation and bias correction VR Pamula, X Sun, SM Kim, F ur Rahman, B Zhang, VS Sathe IEEE Solid-State Circuits Letters 1 (12), 237-240, 2018 | 17 | 2018 |
| Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor SUZ Khan, MS Hossain, FU Rahman, R Zaman, MO Hossen, ... International Journal of Numerical Modelling: Electronic Networks, Devices …, 2015 | 17 | 2015 |
| A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0 V cortex-M0 processor X Sun, S Kim, F ur Rahman, VR Pamula, X Li, N John, VS Sathe 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 302-304, 2018 | 15 | 2018 |
| An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor X Sun, F ur Rahman, VR Pamula, S Kim, X Li, N John, VS Sathe IEEE Journal of Solid-State Circuits 54 (11), 3215-3225, 2019 | 14 | 2019 |
| An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM cortex M0 processor FU Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ... 2018 IEEE Symposium on VLSI Circuits, 65-66, 2018 | 13 | 2018 |
| 19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58 V Microprocessor in 65nm CMOS F ur Rahman, R Pamula, A Boora, X Sun, V Sathe 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 312-314, 2019 | 12 | 2019 |
| Quasi-resonant clocking: Continuous voltage-frequency scalable resonant clocking system for dynamic voltage-frequency scaling systems F ur Rahman, V Sathe IEEE Journal of Solid-State Circuits 53 (3), 924-935, 2018 | 10 | 2018 |
| 19.6 Voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2 V DVFS system FU Rahman, VS Sathe 2016 IEEE International Solid-State Circuits Conference (ISSCC), 334-335, 2016 | 10 | 2016 |
| Analytical modeling of gate capacitance and drain current of gate-all-around InxGa1−xAs nanowire MOSFET SUZ Khan, MS Hossain, MO Hossen, FU Rahman, R Zaman, ... 2014 2nd International Conference on Electronic Design (ICED), 89-93, 2014 | 10 | 2014 |
| Computational locking: Accelerating lock-times in all-digital PLLs F ur Rahman, GF Taylor, VS Sathe 2017 Symposium on VLSI Circuits, C184-C185, 2017 | 6 | 2017 |
| Capacitance-voltage characteristics of gate-all-around InxGa1-xAs nanowire transistor QDM Khosru, SUZ Khan, MS Hossain, FU Rahman, MO Hossen, ... ECS Transactions 53 (1), 169, 2013 | 6 | 2013 |
| Computationally enabled minimum total energy tracking for a performance regulated sub-threshold microprocessor in 65-nm CMOS F ur Rahman, R Pamula, VS Sathe IEEE Journal of Solid-State Circuits 55 (2), 494-504, 2019 | 5 | 2019 |
| Uncoupled mode space approach towards transport modeling of Gate-All-Around InxGa1−xAs nanowire MOSFET SUZ Khan, MS Hossain, FU Rahman, R Zaman, MO Hossen, ... 8th International Conference on Electrical and Computer Engineering, 100-103, 2014 | 4 | 2014 |
| Characterization of interface trap density of In-rich InGaAs Gate-all-around nanowire MOSFETs FU Rahman, MS Hossain, SUZ Khan, R Zaman, MO Hossen, ... 2012 7th International Conference on Electrical and Computer Engineering …, 2012 | 3 | 2012 |
| Self-consistent determination of threshold voltage of In-rich Gate-All-Around InxGa1−xAs nanowire transistor incorporating quantum mechanical effect R Zaman, SUZ Khan, MS Hossain, FU Rahman, MO Hossen, ... 2012 7th International Conference on Electrical and Computer Engineering …, 2012 | 3 | 2012 |
| Variable-length clock stretcher with correction for glitches due to phase detector offset F Ur Rahman, JU Shin US Patent 11,239,846, 2022 | 2 | 2022 |
| Ballistic performance limit and gate leakage modeling of Rectangular Gate-all-around InGaAs Nanowire Transistors with ALD Al2O3 as Gate Dielectric MO Hossen, MS Hossain, SUZ Khan, FU Rahman, R Zaman, ... 2012 IEEE International Conference on Electron Devices and Solid State …, 2012 | 2 | 2012 |
Venkata Rajesh PamulaUniversity of Washington Seattle在 uw.edu 的电子邮件经过验证
Venkata Rajesh PamulaUniversity of Washington Seattle在 uw.edu 的电子邮件经过验证
Saeed-Uz-Zaman KhanPrinceton University在 eee.buet.ac.bd 的电子邮件经过验证