Using cache memory to reduce processor-memory traffic JR Goodman Proceedings of the 10th annual international symposium on Computer …, 1983 | 791 | 1983 |
Speculative lock elision: Enabling highly concurrent multithreaded execution R Rajwar, JR Goodman Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001 | 661 | 2001 |
Memory bandwidth limitations of future microprocessors D Burger, JR Goodman, A Kägi ACM SIGARCH Computer Architecture News 24 (2), 78-89, 1996 | 643 | 1996 |
Cache consistency and sequential consistency JR Goodman University of Wisconsin-Madison Department of Computer Sciences, 1991 | 473 | 1991 |
Transactional lock-free execution of lock-based programs R Rajwar, JR Goodman ACM SIGOPS Operating Systems Review 36 (5), 5-17, 2002 | 448 | 2002 |
Efficient synchronization primitives for large-scale cache-coherent multiprocessors JR Goodman, MK Vernon, PJ Woest Proceedings of the third international conference on Architectural support …, 1989 | 433 | 1989 |
Code scheduling and register allocation in large basic blocks JR Goodman, WC Hsu ACM International Conference on Supercomputing 25th Anniversary Volume, 88-98, 1988 | 379 | 1988 |
The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor JR Goodman, PJ Woest ACM SIGARCH Computer Architecture News 16 (2), 422-431, 1988 | 275 | 1988 |
Hypertree: A multiprocessor interconnection topology Sequin IEEE Transactions on Computers 100 (12), 923-933, 1981 | 236 | 1981 |
PIPE: a VLSI decoupled architecture JR Goodman, J Hsieh, K Liou, AR Pleszkun, PB Schechter, HC Young ACM SIGARCH Computer Architecture News 13 (3), 20-27, 1985 | 174 | 1985 |
System and method for performing incremental register checkpointing in transactional memory MS Moir, D Dice, DS Nussbaum, JR Goodman US Patent 8,560,816, 2013 | 163 | 2013 |
Concurrent execution of critical sections by eliding ownership of locks R Rajwar, JR Goodman US Patent 7,120,762, 2006 | 163 | 2006 |
Billion-transistor architectures D Burger, JR Goodman Computer 30 (09), 46-49, 1997 | 157 | 1997 |
Coherency for multiprocessor virtual address caches JR Goodman ACM SIGARCH Computer Architecture News 15 (5), 72-81, 1987 | 143 | 1987 |
Improving CC-NUMA performance using instruction-based prediction S Kaxiras, JR Goodman Proceedings Fifth International Symposium on High-Performance Computer …, 1999 | 132 | 1999 |
The impact of pipelined channels on k-ary n-cube networks SL Scott, JR Goodman IEEE Transactions on Parallel and Distributed Systems 5 (1), 2-16, 1994 | 132 | 1994 |
Instruction cache replacement policies and organizations Goodman IEEE Transactions on Computers 100 (3), 234-241, 1985 | 116 | 1985 |
The declining effectiveness of dynamic caching for general-purpose microprocessors DC Burger, JR Goodman, A Kagi University of Wisconsin-Madison Department of Computer Sciences, 1995 | 114 | 1995 |
Efficient synchronization: Let them eat QOLB A Kägi, D Burger, JR Goodman Proceedings of the 24th annual international symposium on Computer …, 1997 | 113 | 1997 |
Performance of the SCI Ring SL Scott, JR Goodman, MK Vernon Proceedings of the 19th Annual International Symposium on Computer …, 1992 | 111 | 1992 |