| RICE: Rapid interconnect circuit evaluation using AWE CL Ratzlaff, LT Pillage IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994 | 247 | 1994 |
| RICE: Rapid interconnect circuit evaluator CL Ratzlaff, N Gopal, LT Pillage Proceedings of the 28th ACM/IEEE Design Automation Conference, 555-560, 1991 | 208 | 1991 |
| Method and apparatus for simulating a microelectric interconnect circuit LT Pillage, CL Ratzlaff, N Gopal US Patent 5,379,231, 1995 | 118 | 1995 |
| Modeling the RC-interconnect effects in a hierarchical timing analyzer CL Ratzlaff, S Pullela, LT Pillage 1992 Proceedings of the IEEE Custom Integrated Circuits Conference, 15.6. 1 …, 1992 | 72 | 1992 |
| Apparatus and methods for simulation of electronic circuitry JF Croix, C Ratzlaff US Patent 7,444,604, 2008 | 24 | 2008 |
| Constrained approximation of dominant time constant (s) in RC circuit delay models N Gopal, C Ratzlaff, LT Pillage Proc. 13th IMACS World Congress Comp. App. Math, 1991 | 20 | 1991 |
| Apparatus and methods for compiled static timing analysis C Ratzlaff US Patent 7,155,691, 2006 | 16 | 2006 |
| Interconnect model compiler CL Ratzlaff, JF Croix, R Jones US Patent 6,766,506, 2004 | 9 | 2004 |
| High speed memory simulation C Oh, JF Croix, CL Ratzlaff, RD Acosta US Patent 8,275,597, 2012 | 4 | 2012 |
| Using impedance (Z) parameters to augment circuit simulation CL Ratzlaff US Patent 7,970,591, 2011 | 2 | 2011 |
