| 6.4 Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers Y Lee, H Yoo, I Yoo, IC Park Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012 | 85 | 2012 |
| Energy-Efficient floating-point MFCC extraction architecture for speech recognition systems J Jo, H Yoo, IC Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 754-758, 2016 | 55 | 2016 |
| Partially parallel encoder architecture for long polar codes H Yoo, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 62 (3), 306-310, 2015 | 52 | 2015 |
| Efficient sorting architecture for successive-cancellation-list decoding of polar codes BY Kong, H Yoo, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 63 (7), 673-677, 2016 | 51 | 2016 |
| Efficient parallel architecture for linear feedback shift registers J Jung, H Yoo, Y Lee, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 62 (11), 1068-1072, 2015 | 48 | 2015 |
| High-throughput and low-complexity BCH decoding architecture for solid-state drives Y Lee, H Yoo, I Yoo, IC Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5 …, 2014 | 40 | 2014 |
| Low-complexity parallel Chien search structure using two-dimensional optimization Y Lee, H Yoo, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 58 (8), 522-526, 2011 | 38 | 2011 |
| Area-efficient multimode encoding architecture for long BCH codes H Yoo, J Jung, J Jo, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 60 (12), 872-876, 2013 | 35 | 2013 |
| A 2.74-pJ/bit, 17.7-Gb/s iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash memory Y Lee, H Yoo, J Jung, J Jo, IC Park IEEE Journal of Solid-State Circuits 48 (10), 2531-2540, 2013 | 34 | 2013 |
| 7.3 Gb/s universal BCH encoder and decoder for SSD controllers H Yoo, Y Lee, IC Park Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, 37-38, 2014 | 30 | 2014 |
| Efficient pruning for successive-cancellation decoding of polar codes H Yoo, IC Park IEEE Communications Letters 20 (12), 2362-2365, 2016 | 22 | 2016 |
| Small-area parallel syndrome calculation for strong BCH decoding Y Lee, H Yoo, IC Park Acoustics, Speech and Signal Processing (ICASSP), 2012 IEEE International …, 2012 | 18 | 2012 |
| Area-efficient syndrome calculation for strong BCH decoding H Yoo, Y Lee, IC Park Electronics letters 47 (2), 107-108, 2011 | 14 | 2011 |
| Modified Viterbi Scoring for HMM-Based Speech Recognition J Jo, HG Kim, IC Park, BC Jung, H Yoo INTELLIGENT AUTOMATION AND SOFT COMPUTING 25 (2), 351-358, 2019 | 12 | 2019 |
| Low-power parallel Chien search architecture using a two-step approach H Yoo, Y Lee, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 63 (3), 269-273, 2016 | 11 | 2016 |
| Reverse Engineering for Xilinx FPGA Chips using ISE Design Tools HY Yoo, SY Choi, JW Park Journal of Integrated Circuits and Systems 6 (1), 2020 | 9 | 2020 |
| Area-Efficient Fault Tolerant Design for Finite State Machines S Choi, J Park, H Yoo | 8* | |
| Area-Efficient Error Detection Structure for Linear Feedback Shift Registers H Shin, S Choi, J Park, BY Kong, H Yoo Electronics 9 (1), 195, 2020 | 6 | 2020 |
| Area-Efficient Early-Termination Technique for Belief-Propagation Polar Decoders S Choi, H Yoo Electronics 8 (9), 1001, 2019 | 5 | 2019 |
| A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process Y Lee, H Yoo, IC Park Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, 85-86, 2013 | 3 | 2013 |
