| A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications S Lee, K Kim, S Oh, J Park, G Hong, D Ka, K Hwang, J Park, K Kang, ... ISSCC, 2022 | 73 | 2022 |
| A 4.8 Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface WY Shin, GM Hong, H Lee, JD Han, S Kim, KS Park, DH Lim, JH Chun, ... 2011 IEEE International Solid-State Circuits Conference, 494-496, 2011 | 32 | 2011 |
| System architecture and software stack for GDDR6-AiM Y Kwon, K Vladimir, N Kim, W Shin, J Won, M Lee, H Joo, H Choi, G Kim, ... 2022 IEEE Hot Chips 34 Symposium (HCS), 1-25, 2022 | 17 | 2022 |
| High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line M Kim, WY Shin, GM Hong, J Park, JH Chae, N Xing, JK Woo, S Kim 2013 Proceedings of the ESSCIRC (ESSCIRC), 311-314, 2013 | 16 | 2013 |
| Bitline techniques with dual dynamic nodes for low-power register files R Singh, GM Hong, S Kim IEEE Transactions on Circuits and Systems I: Regular Papers 60 (4), 965-974, 2013 | 13 | 2013 |
| 266–2133 MHz phase shifter using all‐digital delay‐locked loop and triangular‐modulated phase interpolator for LPDDR4X interface JH Chae, M Kim, H Ko, Y Jeong, J Park, GM Hong, DK Jeong, S Kim Electronics Letters 53 (12), 766-768, 2017 | 12 | 2017 |
| A PVT-compensated 2.2 to 3.0 GHz digitally controlled oscillator for all-digital PLL A Kavala, W Bae, S Kim, GM Hong, H Chi, S Kim, DK Jeong JSTS: Journal of Semiconductor Technology and Science 14 (4), 484-494, 2014 | 12 | 2014 |
| Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers R Singh, GM Hong, M Kim, J Park, WY Shin, S Kim Integration 45 (3), 253-262, 2012 | 12 | 2012 |
| A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications S Kim, JK Woo, WY Shin, GM Hong, H Lee, H Lee, S Kim IEEE/ACM International Symposium on Low Power Electronics and Design, 347-350, 2011 | 12 | 2011 |
| A 1ynm 1.25 v 8gb 16gb/s/pin gddr6-based accelerator-in-memory supporting 1tflops mac operation and various activation functions for deep learning application D Kwon, S Lee, K Kim, S Oh, J Park, GM Hong, D Ka, K Hwang, J Park, ... IEEE Journal of Solid-State Circuits 58 (1), 291-302, 2022 | 11 | 2022 |
| A 1ynm 1.25 V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. In 2022 IEEE … S Lee, K Kim, S Oh, J Park, G Hong, D Ka, K Hwang, J Park, K Kang, ... IEEE, 2022 | 11 | 2022 |
| 4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver WY Shin, GM Hong, H Lee, JD Han, KS Park, DH Lim, S Kim, D Shim, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (5 …, 2013 | 11 | 2013 |
| A 4266 Mb/s/pin LPDDR4 interface with an asynchronous feedback CTLE and an adaptive 3-step eye detection algorithm for memory controller M Kim, JH Chae, S Choi, GM Hong, H Ko, DK Jeong, S Kim IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 1894-1898, 2018 | 10 | 2018 |
| A fast-acquisition PLL using split half-duty sampled feedforward loop filter WY Shin, M Kim, GM Hong, S Kim IEEE Transactions on Consumer Electronics 56 (3), 1856-1859, 2010 | 10 | 2010 |
| 0.11-2.5 GHz all-digital DLL for mobile memory interface with phase sampling window adaptation to reduce jitter accumulation JH Chae, M Kim, GM Hong, J Park, H Ko, WY Shin, H Chi, DK Jeong, ... JSTS: Journal of Semiconductor Technology and Science 17 (3), 411-424, 2017 | 7 | 2017 |
| A 1.74 mW/GHz 0.11–2.5 GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers JH Chae, GM Hong, J Park, M Kim, H Ko, WY Shin, H Chi, DK Jeong, ... 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 7 | 2015 |
| A 3.2 Gb/s 16-channel transmitter for intra-panel interfaces, with independently controllable output swing, common-mode voltage, and equalization JH Chae, M Kim, GM Hong, J Park, S Kim IEEE Access 6, 78055-78064, 2018 | 6 | 2018 |
| A 10-Mbps 0.8-pJ/bit referenceless clock and data recovery circuit for optically controlled neural interface system S Kim, JK Woo, WY Shin, GM Hong, H Lee, H Lee, S Kim IEEE Transactions on Circuits and Systems II: Express Briefs 60 (1), 6-10, 2013 | 6 | 2013 |
| Integrated circuit with ring oscillator KD Kim, S Kim, H Gi-Moon US Patent 9,071,232, 2015 | 5 | 2015 |
| A 3.2-GHz quadrature error corrector for DRAM transmitters, using replica serializers and pulse-shrinking delay lines H Ko, C Hyun, JH Chae, GM Hong, S Kim IEEE Solid-State Circuits Letters 3, 38-41, 2020 | 4 | 2020 |
