| Fault tolerant carry save adders-A NMR configuration approach S Radhakrishnan, T Nirmalraj, S Ashwin, V Elamaran, RK Karn 2018 International Conference on Control, Power, Communication and Computing …, 2018 | 11 | 2018 |
| An enhanced Gate Diffusion Input technique for low power applications S Radhakrishnan, T Nirmalraj Microelectronics Journal 93, 104621, 2019 | 5 | 2019 |
| Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA T Nirmalraj, S Radhakrishnan, SK Pandiyan IET Computers & Digital Techniques 15 (5), 362-371, 2021 | 4 | 2021 |
| An efficient design for area-efficient truncated adaptive booth multiplier for signal processing applications S Radhakrishnan, RK Karn, T Nirmalraj Journal of Circuits, Systems and Computers 30 (03), 2150037, 2021 | 4 | 2021 |
| Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology T Nirmalraj, S Radhakrishnan, RK Karn, SK Pandiyan 2017 IEEE International Conference on Power, Control, Signals and …, 2017 | 2 | 2017 |
| Low latency power aware selfchecking based CSA for sequential multiplier S Radhakrishnan, T Nirmalraj, RK Karn, SK Pandiyan 2017 IEEE International Conference on Power, Control, Signals and …, 2017 | 2 | 2017 |
