| DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 7 | 2023 |
| Variation-aware delay fault testing for carbon-nanotube FET circuits S Banerjee, A Chaudhuri, A Ning, K Chakrabarty IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (2), 409-422, 2021 | 7 | 2021 |
| Supply chain aware computer architecture A Ning, G Tziantzioulis, D Wentzlaff Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 5 | 2023 |
| Duet: Creating Harmony between Processors and Embedded FPGAs A Li, A Ning, D Wentzlaff 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 5 | 2023 |
| A hardware evaluation framework for large language model inference H Zhang, A Ning, R Prabhakar, D Wentzlaff arXiv preprint arXiv:2312.03134, 2023 | 4 | 2023 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference H Zhang, A Ning, RB Prabhakar, D Wentzlaff | | |
David WentzlaffAssociate Professor of Electrical Engineering, Princeton University在 princeton.edu 的电子邮件经过验证
