| A 0.8-V, 1.54-pJ/940-MHz dual-mode logic-based 16× 16-b booth multiplier in 16-nm FinFET N Shavit, I Stanger, R Taco, M Lanuzza, A Fish IEEE Solid-State Circuits Letters 3, 314-317, 2020 | 21 | 2020 |
| Silicon evaluation of multimode dual mode logic for PVT-aware datapaths I Stanger, N Shavit, R Taco, M Lanuzza, A Fish IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1639-1643, 2020 | 11 | 2020 |
| Dual mode logic address decoder L Yavits, R Taco, N Shavit, I Stanger, A Fish 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 10 | 2020 |
| Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance I Stanger, N Shavit, R Taco, L Yavits, M Lanuzza, A Fish 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 6 | 2020 |
| Efficiency of dual mode logic in nanoscale technology nodes N Shavit, R Taco, A Fish 2018 IEEE International Conference on the Science of Electrical Engineering …, 2018 | 6 | 2018 |
| A method for mitigation of droop timing errors including a 500 MHz droop detector and dual mode logic Y Shifman, I Stanger, N Shavit, R Taco, A Fish, J Shor IEEE Journal of Solid-State Circuits 57 (2), 596-608, 2021 | 5 | 2021 |
| Process variation-aware datapath employing dual mode logic N Shavit, I Stanger, R Taco, A Fish 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 5 | 2018 |
| Revisiting Dynamic Logic—A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies I Stanger, N Roknian, N Shavit, Y Shoshan, Y Weizman, A Teman, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 2 | 2023 |
| FlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic I Stanger, N Shavit, R Taco, M Lanuzza, L Yavits, I Levi, A Fish IEEE Solid-State Circuits Letters 6, 73-76, 2023 | 2 | 2023 |
| Method for mitigation of droop timing errors including a droop detector and dual mode logic J Shor, Y Schifmann, I Stanger, N Shavit, ERT Lasso, A Fish US Patent App. 17/529,456, 2022 | 2 | 2022 |
| Programmable All-in-One 4x8-/2x16-/1x32-bits Dual Mode Logic Multiplier in 16 nm FinFET with Semi-Automatic Flow N Shavit, I Stanger, R Taco, A Fish, I Levi IEEE Access, 2023 | 1 | 2023 |
| Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology R Taco, L Yavits, N Shavit, I Stanger, M Lanuzza, A Fish 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 1 | 2020 |
| Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications N Shavit, I Stanger, R Taco, L Yavits, A Fish 2024 19th Conference on Ph. D Research in Microelectronics and Electronics …, 2024 | | 2024 |
| Live Demonstration: A 0.8 V, 1.54 pJ/940 MHz Dual Mode Logic-based 16x16-bit Booth Multiplier in 16-nm FinFET N Shavit, I Stanger, R Taco, M Lanuzza, A Fish 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2021 | | 2021 |
| Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths I Stanger, N Shavit, R Taco, M Lanuzza, A Fish 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2021 | | 2021 |
| SPECIAL ISSUE ON THE 2023 LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS) I Stanger, N Roknian, N Shavit, Y Shoshan, Y Weizman, A Teman, ... | | |
