| Low power aging-aware register file design by duty cycle balancing S Wang, T Jin, C Zheng, G Duan 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 546-549, 2012 | 47 | 2012 |
| Exploiting narrow-width values for improving non-volatile cache lifetime G Duan, S Wang 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 21 | 2014 |
| Word-and partition-level write variation reduction for improving non-volatile cache lifetime S Wang, G Duan, Y Li, Q Dong ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (1 …, 2017 | 11 | 2017 |
| Combating nbti-induced aging in data caches S Wang, G Duan, C Zheng, T Jin Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 11 | 2013 |
| On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors S Wang, G Duan Microprocessors and Microsystems 39 (8), 686-692, 2015 | 10 | 2015 |
| On the measurement of safe fault failure rates in high-performance compute processors R Bramley, Y Huang, G Duan, N Saxena, P Racunas 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 3 | 2020 |
| Low power aging-aware on-chip memory structure design by duty cycle balancing S Wang, T Jin, C Zheng, G Duan Journal of Circuits, Systems and Computers 25 (09), 1650115, 2016 | 2 | 2016 |
| Combating NBTI-induced Aging in Data Caches G Duan, C Zheng, T Jin, S Wang | | |
| Aging-Aware SRAM Instruction Cache Design with Duty Cycle Balancing S Wang, T Jin, C Zhen, G Duan | | |
