| A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin, S Wei ACM Computing Surveys (CSUR) 52 (6), 1-39, 2019 | 188 | 2019 |
| Low-Power Reconfigurable Processor Utilizing Variable Dual J Zhu, L Liu, S Yin, S Wei IEEE Transactions on Circuits and Systems II: Express Briefs 60 (4), 217-221, 2013 | 17 | 2013 |
| Upward packet popup for deadlock freedom in modular chiplet-based systems Y Wu, L Wang, X Wang, J Han, J Zhu, H Jiang, S Yin, S Wei, L Liu 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 15 | 2022 |
| A general pattern-based dynamic compilation framework for coarse-grained reconfigurable architectures X Man, L Liu, J Zhu, S Wei Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 12 | 2019 |
| TLIA: Efficient reconfigurable architecture for control-intensive kernels with triggered-long-instructions L Liu, J Wang, J Zhu, C Deng, S Yin, S Wei IEEE Transactions on Parallel and Distributed Systems 27 (7), 2143-2154, 2015 | 12 | 2015 |
| A hybrid reconfigurable architecture and design methods aiming at control-intensive kernels J Zhu, L Liu, S Yin, X Yang, S Wei IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (9 …, 2014 | 11 | 2014 |
| Architecture, challenges and applications of dynamic reconfigurable computing Y Lu, L Liu, J Zhu, S Yin, S Wei Journal of Semiconductors 41 (2), 021401, 2020 | 10 | 2020 |
| A fast application-based supply voltage optimization method for dual voltage FPGA J Zhu, L Pan, Y Yan, D Wu, H He IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (12 …, 2014 | 9 | 2014 |
| An elastic task scheduling scheme on coarse-grained reconfigurable architectures L Chen, J Zhu, Y Deng, Z Li, J Chen, X Jiang, S Yin, S Wei, L Liu IEEE Transactions on Parallel and Distributed Systems 32 (12), 3066-3080, 2021 | 8 | 2021 |
| A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect Z Jianfeng, H Hu, W Dong, P Liyang Journal of electronic testing 27, 647-655, 2011 | 8 | 2011 |
| Jintide: Utilizing low-cost reconfigurable external monitors to substantially enhance hardware security of large-scale CPU clusters J Zhu, A Luo, G Li, B Zhang, Y Wang, G Shan, Y Li, J Pan, C Deng, S Yin, ... IEEE Journal of Solid-State Circuits 56 (8), 2585-2601, 2021 | 6 | 2021 |
| Jintide®: a hardware security enhanced server CPU with Xeon® Cores under runtime surveillance by an In-Package dynamically reconfigurable processor L Liu, A Luo, G Li, J Zhu, Y Wang, G Shan, J Pan, S Yin, S Wei 2019 IEEE Hot Chips 31 Symposium (HCS), 1-25, 2019 | 6 | 2019 |
| Acceleration of control flows on reconfigurable architecture with a composite method J Wang, L Liu, J Zhu, S Yin, S Wei Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 6 | 2015 |
| Mapzero: Mapping for coarse-grained reconfigurable architectures with reinforcement learning and monte-carlo tree search X Kong, Y Huang, J Zhu, X Man, Y Liu, C Feng, P Gou, M Tang, S Wei, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 5 | 2023 |
| QuickFPS: Architecture and algorithm co-design for farthest point sampling in large-scale point clouds M Han, L Wang, L Xiao, H Zhang, C Zhang, X Xu, J Zhu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 5 | 2023 |
| M2STaR: A Multi-Mode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures X Kong, J Zhu, X Man, G Song, Y Huang, C Deng, P Gou, S Yin, S Wei, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 5 | 2023 |
| CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process X Man, J Zhu, G Song, S Yin, S Wei, L Liu Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 5 | 2022 |
| Dynamic-II pipeline: compiling loops with irregular branches on static-scheduling CGRA B Yuan, J Zhu, X Man, Z Ma, S Yin, S Wei, L Liu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 5 | 2021 |
| Pattern-based dynamic compilation system for CGRAs with online configuration transformation L Liu, X Man, J Zhu, S Yin, S Wei IEEE Transactions on Parallel and Distributed Systems 31 (12), 2981-2994, 2020 | 5 | 2020 |
| An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance C Deng, M Zhu, J Yang, Y Wu, J He, B Yang, J Zhu, S Yin, S Wei, L Liu Science China. Information Sciences 65 (4), 149404, 2022 | 2 | 2022 |
