| Fast and accurate performance simulation of embedded software for MPSoC E Cheung, H Hsieh, F Balarin Proceedings of the 2009 Asia and South Pacific Design Automation Conference …, 2009 | 30 | 2009 |
| Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip E Cheung, H Hsieh, F Balarin High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE …, 2007 | 28 | 2007 |
| Memory subsystem simulation in software TLM/T models E Cheung, H Hsieh, F Balarin Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific …, 2009 | 25 | 2009 |
| Framework for fast and accurate performance simulation of multiprocessor systems E Cheung, H Hsieh, F Balarin High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE …, 2007 | 17 | 2007 |
| Runtime deadlock analysis for system level design E Cheung, X Chen, H Hsieh, A Davare, A Sangiovanni-Vincentelli, ... Design Automation for Embedded Systems 13 (4), 287, 2009 | 11 | 2009 |
| Runtime deadlock analysis of SystemC designs E Cheung, P Satapathy, V Pham, H Hsieh, X Chen High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE …, 2006 | 10 | 2006 |
| Bridging RTL and gate: correlating different levels of abstraction for design debugging E Cheung, X Chen, F Tsai, YC Hsu, H Hsieh High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE …, 2007 | 7 | 2007 |
| Software optimization for MPSoC: a mpeg-2 decoder case study E Cheung, H Hsieh, F Balarin Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware …, 2008 | 1 | 2008 |
| Smart home connected device contextual learning using audio commands E Cheung US Patent US20160225372A1, 2016 | | 2016 |
| Partial order method for timed simulation of system-level MPSoC designs E Cheung, H Hsieh, F Balarin Proceedings of the 2009 Asia and South Pacific Design Automation Conference …, 2009 | | 2009 |
| MPSoC simulation and implementation of KPN applications CS Cheung University of California, Riverside, 2009 | | 2009 |
