| Challenges and trends of SRAM-based computing-in-memory for AI edge devices CJ Jhang, CX Xue, JM Hung, FC Chang, MF Chang IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 1773-1786, 2021 | 164 | 2021 |
| 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021 | 155 | 2021 |
| A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5-65.0 TOPS/W for tiny-Al edge devices WS Khwa, YC Chiu, CJ Jhang, SP Huang, CY Lee, TH Wen, FC Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 69 | 2022 |
| A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices JM Hung, CX Xue, HY Kao, YH Huang, FC Chang, SP Huang, TW Liu, ... Nature Electronics 4 (12), 921-930, 2021 | 62 | 2021 |
| Challenges and trends of nonvolatile in-memory-computation circuits for AI edge devices JM Hung, CJ Jhang, PC Wu, YC Chiu, MF Chang IEEE Open Journal of the Solid-State Circuits Society 1, 171-183, 2021 | 43 | 2021 |
| A 8-b-precision 6T SRAM computing-in-memory macro using segmented-bitline charge-sharing scheme for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hong, ... IEEE Journal of Solid-State Circuits 58 (3), 877-892, 2022 | 29 | 2022 |
| A nonvolatile Al-edge processor with 4MB SLC-MLC hybrid-mode ReRAM compute-in-memory macro and 51.4-251TOPS/W WH Huang, TH Wen, JM Hung, WS Khwa, YC Lo, CJ Jhang, HH Hsu, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 15-17, 2023 | 25 | 2023 |
| A relaxed quantization training method for hardware limitations of resistive random access memory (ReRAM)-based computing-in-memory WC Wei, CJ Jhang, YR Chen, CX Xue, SH Sie, JL Lee, HW Kuo, CC Lu, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020 | 16 | 2020 |
| A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme HH Hsu, TH Wen, WH Huang, WS Khwa, YC Lo, CJ Jhang, YH Chin, ... IEEE Journal of Solid-State Circuits, 2023 | 4 | 2023 |
| Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing TH Wen, JM Hung, WH Huang, CJ Jhang, YC Lo, HH Hsu, ZE Ke, ... Science 384 (6693), 325-332, 2024 | 3 | 2024 |
| Challenges of computation-in-memory circuits for AI edge applications CJ Jhang, PC Chen, MF Chang 2021 International Symposium on VLSI Technology, Systems and Applications …, 2021 | 3 | 2021 |
| A 22nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications CJ Jhang, WS Khwa, PC Wu, AS Lele, PS Wu, CE Ke, TC Chiu, YC Hung, ... IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2024 | | 2024 |
| A 22nm Nonvolatile AI-Edge Processor with 21.4 TFLOPS/W using 47.25 Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro DQ You, WS Khwa, JJ Wu, CJ Jhang, GY Lin, PJ Chen, TC Chiu, FY Chen, ... 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024 | | 2024 |
| Memory device and operating method thereof WS Khwa, MF Chang, JJ Wu, CJ Jhang US Patent App. 18/163,877, 2024 | | 2024 |
| Computing circuit, computing method, and decoder WS Khwa, CJ Jhang, YL Lu, JJ Wu, MF Chang US Patent App. 18/163,878, 2024 | | 2024 |
| Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips HH Hsu, TH Wen, PC Wu, CJ Jhang, DQ You, PC Chen, MF Chang 2023 IEEE 66th International Midwest Symposium on Circuits and Systems …, 2023 | | 2023 |
| Memory structure with input-aware maximum multiply-and-accumulate value zone prediction for computing-in-memory applications and operating method thereof MF Chang, JW Su, JM Hung, CJ Jhang, PC Wu, JS Ren US Patent 11,416,146, 2022 | | 2022 |
