| Design, implementation and comparative analysis of Kogge Stone adder using CMOS and GDI design: a VLSI based approach CN Shilpa, KD Shinde, HV Nithin 2016 8th International Conference on Computational Intelligence and …, 2016 | 16 | 2016 |
| Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology V Muddi, KD Shinde, BK Shivaprasad 2015 International Conference on Control, Instrumentation, Communication and …, 2015 | 13 | 2015 |
| Design of fast and efficient 1-bit full adder and its performance analysis KD Shinde, JC Nidagundi 2014 International Conference on Control, Instrumentation, Communication and …, 2014 | 12 | 2014 |
| Analysis and comparative study of 8-bit adder for embedded application KD Shinde, S Badiger 2015 International Conference on Control, Instrumentation, Communication and …, 2015 | 8 | 2015 |
| Performance analysis and implementation of array multiplier using various full adder designs for DSP applications: A VLSI based approach KA Asha, KD Shinde Intelligent Systems Technologies and Applications 2016, 731-742, 2016 | 6 | 2016 |
| Impact of VLSI design techniques on implementation of parallel prefix adders KD Shinde, K Amit Kumar, CN Shilpa Soft Computing Systems: Second International Conference, ICSCS 2018, Kollam …, 2018 | 4 | 2018 |
| A Novel Approach to Design Braun Array Multiplier Using Parallel Prefix Adders for Parallel Processing Architectures: - A VLSI Based Approach KD Shinde, K Amit Kumar, DS Rashmi, R Sadiya Rukhsar, HR Shilpa, ... Soft Computing Systems: Second International Conference, ICSCS 2018, Kollam …, 2018 | 4 | 2018 |
| Implementation of Low Cost, Reliable, and Advanced Control with Head Movement, Wheelchair for Physically Challenged People KD Shinde, S Tarannum, T Veerabhadrappa, E Gagan, PV Kumar Progress in Advanced Computing and Intelligent Engineering, 313-328, 2017 | 4 | 2017 |
| Design and implementation of parallel floating point matrix multiplier for quaternion computation BK Shivaprasad, KD Shinde, V Muddi 2015 International Conference on Control, Instrumentation, Communication and …, 2015 | 4 | 2015 |
| Modeling, Design and Performance Analysis of Various 8-bit Adders for Embedded Applications KD Shinde NMIT, ERCICA-14 2 (1), 8, 2014 | 4 | 2014 |
| Comparative analysis of 8-bit adders for embedded applications KD Shinde, CN Jayashree Proceedings of the IJERT in National Conference on “Real Time System (NCRTS …, 2014 | 4 | 2014 |
| Bottlenecks in finite impulse response filter architectures on a reconfigurable platform KD Shinde, C Vijaya Recent Advances in Artificial Intelligence and Data Engineering: Select …, 2022 | 2 | 2022 |
| Modeling of adders using CMOS and GDI logic for multiplier applications: A VLSI based approach DS Rashmi, RS Rukhsar, HR Shilpa, CR Vidyashree, KD Shinde, ... 2016 International Conference on Circuit, Power and Computing Technologies …, 2016 | 2 | 2016 |
| Analysis, Design and Implementation of Full Adder for Systolic Array Based Architectures – A VLSI Based Approach AKA Kunjan D Shinde IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 6 (3), PP 73-77, 2016 | 2* | 2016 |
| Modeling and Comparative Analysis of Logic Gates for Adder and Multiplier Applications-A VLSI based approach MS C N, MKD Shinde, Mr Nithin HV IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 6 (13), 67-72, 2016 | 1* | 2016 |
| Modeling and Comparative Analysis of Logic Gates for Adder and Multiplier Applications -A VLSI based approach SCN Kunjan D Shinde IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 6 (3), PP 67-72, 2016 | 1* | 2016 |
| Optimizing Parallel FIR Filter Architecture for Time-Sensitive Applications: A Design Approach for High-Throughput and Area Efficiency. KD Shinde, C Vijaya International Journal of Intelligent Engineering & Systems 16 (4), 2023 | | 2023 |
| PERFORMANCE ANALYSIS OF NOVEL PARALLEL FIR FILTER ARCHITECTURE FOR NOISE REDUCTION IN ECG SIGNAL PROCESSING FOR TIME CRITICAL APPLICATIONS KD Shinde, C Vijaya Journal of Data Acquisition and Processing 38 (3), 1214, 2023 | | 2023 |
| Denoising of ECG Signal Using Optimized IIR Filter Architecture—A CSD-Based Design KD Shinde, D Khanapure, N Shetti, J Athavani, N Hattiholi International Conference on VLSI, Signal Processing, Power Electronics, IoT …, 2022 | | 2022 |
| Development of Flexible Verification Environment for AMBA APB HV Nithin, KD Shinde JNNCE Journal of Engineering & Management (JJEM) 4 (2), 8, 2021 | | 2021 |
jayashree NidagundiAsst.Professor在 sdmcet.ac.in 的电子邮件经过验证
