| LAYGO2: A custom layout generation engine based on dynamic templates and grids for advanced CMOS technologies T Shin, D Lee, D Kim, G Sung, W Shin, Y Jo, H Park, J Han IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 7 | 2023 |
| 6.8 A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing Hybrid FFE Taps in 40nm J Yang, E Song, S Hong, D Lee, S Lee, H Im, T Shin, J Han 2023 IEEE International Solid-State Circuits Conference (ISSCC), 122-124, 2023 | 7 | 2023 |
| A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits T Shin, J Han 2021 18th International SoC Design Conference (ISOCC), 335-336, 2021 | 2 | 2021 |
| A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology Y Oh, H Im, J Yang, E Song, D Lee, S Lee, T Shin, J Han IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | 1 | 2024 |
| A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids T Shin, D Lee, D Kim, G Sung, W Shin, Y Jo, H Park, J Han arXiv preprint arXiv:2207.11728, 2022 | | 2022 |
Jaeduk HanHanyang University在 eecs.berkeley.edu 的电子邮件经过验证
Jaeduk HanHanyang University在 eecs.berkeley.edu 的电子邮件经过验证