| A turn model based router design for 3D network on chip B Chemli, A Zitouni World Applied Sciences Journal 32 (8), 1499-1505, 2014 | 12 | 2014 |
| Design of a Network on Chip router based on turn model B Chemli, A Zitouni 2015 16th International Conference on Sciences and Techniques of Automatic …, 2015 | 10 | 2015 |
| Architecture and performances comparison of network on chip router for hierarchical mesh topology B Chemli, A Zitouni 2017 International Conference on Engineering & MIS (ICEMIS), 1-4, 2017 | 6 | 2017 |
| Design and evaluation of optimized router pipeline stages for network on chip B Chemli, A Zitouni 2016 International Image Processing, Applications and Systems (IPAS), 1-5, 2016 | 5 | 2016 |
| Design of efficient pipelined router architecture for 3D network on chip B Chemli, A Zitouni, A Coelho, R Velazco International Journal of Advanced Computer Science and Applications 8 (7), 2017 | 3 | 2017 |
| Low Cost Network on Chip Router Design for Torus Topology B Chemli, A Zitouni IJCSNS 17 (5), 287, 2017 | 2 | 2017 |
| Asynchronous dynamic arbiter for network on chip A Zitouni, B Chemli International Journal of Computer Applications in Technology 67 (4), 370-382, 2021 | 1 | 2021 |
Raoul VelazcoTIMA - CNRS在 imag.fr 的电子邮件经过验证
Raoul VelazcoTIMA - CNRS在 imag.fr 的电子邮件经过验证