| Mlperf inference benchmark VJ Reddi, C Cheng, D Kanter, P Mattson, G Schmuelling, CJ Wu, ... 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 471 | 2020 |
| Deep learning with int8 optimization on xilinx devices Y Fu, E Wu, A Sirasao, S Attia, K Khan, R Wittig White Paper, 2016 | 91 | 2016 |
| Mlperf inference benchmark. In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) VJ Reddi, C Cheng, D Kanter, P Mattson, G Schmuelling, CJ Wu, ... IEEE, 2020 | 80 | 2020 |
| Image preprocessing for generalized image processing E Delaye, A Sirasao, A Ng, Y Wu, J Zejda US Patent 11,386,644, 2022 | 64 | 2022 |
| Neural network processing system having multiple processors and a neural network accelerator X Teng, A Ng, A Sirasao, E Delaye US Patent 11,222,256, 2022 | 37 | 2022 |
| Neural network processing system having host controlled kernel acclerators A Ng, J Zejda, E Delaye, X Teng, A Sirasao US Patent 11,568,218, 2023 | 34 | 2023 |
| Static block scheduling in massively parallel software defined hardware systems Y Wu, J Zejda, E Delaye, A Sirasao US Patent App. 15/786,434, 2019 | 30 | 2019 |
| Quantizing convolutional neural networks for low-power high-throughput inference engines SO Settle, M Bollavaram, P D'Alberto, E Delaye, O Fernandez, N Fraser, ... arXiv preprint arXiv:1805.07941, 2018 | 29 | 2018 |
| Multiply and accumulate circuit S Pareek, A Hosangadi, B Tian, A Sirasao, Y Fu, OFC Fernandez, M Wu, ... US Patent 10,747,502, 2020 | 28 | 2020 |
| Fpga based opencl acceleration of genome sequencing software A Sirasao, E Delaye, R Sunkavalli, S Neuendorffer System 128 (8.7), 11, 2015 | 21 | 2015 |
| Xrbench: An extended reality (xr) machine learning benchmark suite for the metaverse H Kwon, K Nair, J Seo, J Yik, D Mohapatra, D Zhan, J Song, P Capak, ... Proceedings of Machine Learning and Systems 5, 1-20, 2023 | 20 | 2023 |
| Host-directed multi-layer neural network processing via per-layer work requests A Ng, E Delaye, J Zejda, A Sirasao US Patent 11,429,848, 2022 | 19 | 2022 |
| 8-bit dot-product acceleration Y Fu, E Wu, A Sirasao Xilinx Inc.: San Jose, CA, USA, 20, 2017 | 17 | 2017 |
| Sparse matrix processing circuitry J Zejda, L Liu, Y Zhou, A Sirasao US Patent 10,572,409, 2020 | 16 | 2020 |
| Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC J Zejda, E Delaye, A Sirasao, Y Wu, A Ng US Patent 10,354,733, 2019 | 15 | 2019 |
| Deep learning challenges and solutions with xilinx fpgas E Delaye, A Sirasao, C Dudha, S Das 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 908-913, 2017 | 15 | 2017 |
| Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions J Zejda, E Delaye, Y Wu, A Ng, A Sirasao, KK Dao, CJ Case US Patent 11,204,747, 2021 | 11 | 2021 |
| Loop optimization for implementing circuit designs in hardware A Hosangadi, S Datta, A Gayasen, A Sirasao US Patent 10,331,836, 2019 | 11 | 2019 |
| Precision medicine and FPGA technology: Challenges and opportunities B Hill, J Smith, G Srinivasa, K Sonmez, A Sirasao, A Gupta, M Mukherjee 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 11 | 2017 |
| Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions A Ng, E Delaye, E Ghasemi, X Teng, J Zejda, Y Wu, S Settle, A Sirasao US Patent 11,620,490, 2023 | 10 | 2023 |
Ehsan GhasemiStanford University在 stanford.edu 的电子邮件经过验证
