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Gianluca Boselli
Gianluca Boselli
在 ti.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies
JC Smith, G Boselli
2003 Electrical Overstress/Electrostatic Discharge Symposium, 1-9, 2003
1242003
RF CMOS on high-resistivity substrates for system-on-chip applications
K Benaissa, JY Yang, D Crenshaw, B Williams, S Sridhar, J Ai, G Boselli, ...
IEEE Transactions on Electron Devices 50 (3), 567-576, 2003
1052003
Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window
G Boselli, J Rodriguez, C Duvvury, J Smith
2005 Electrical Overstress/Electrostatic Discharge Symposium, 1-10, 2005
642005
Latch-up in 65nm CMOS technology: a scaling perspective
G Boselli, V Reddy, C Duvvury
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005
552005
PMOS electrostatic discharge (ESD) protection device
G Boselli, VK Reddy, EA Amerasekera
US Patent 7,196,887, 2007
532007
3B. 6 A Low Leakage Low Cost-PMOS Based Power Supply Clamp with Active Feedback for ESD Protection in 65nm CMOS Technologies
JC Smith, RA Cline, G Boselli
ELECTRICAL OVERSTRESS ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 2005, 298, 2005
452005
Drain extended nMOS high current behavior and ESD protection strategy for HV applications in Sub-100nm CMOS technologies
G Boselli, V Vassilev, C Duvvury
2007 IEEE International Reliability Physics Symposium Proceedings. 45th …, 2007
402007
The relevance of long-duration TLP stress on system level ESD design
G Boselli, A Salman, J Brodsky, H Kunz
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 1-10, 2010
382010
The effects of angle of incidence and temperature on latchup in 65 nm technology
JM Hutson, JD Pellish, G Boselli, R Baumann, RA Reed, RD Schrimpf, ...
IEEE Transactions on Nuclear Science 54 (6), 2541-2546, 2007
342007
Evidence for lateral angle effect on single-event latchup in 65 nm SRAMs
JM Hutson, JA Pellish, AD Tipton, G Boselli, MA Xapsos, H Kim, ...
IEEE Transactions on Nuclear Science 56 (1), 208-213, 2009
312009
ESD and latch-up reliability for nanometer CMOS technologies
C Duvvury, G Boselli
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
312004
0.1/spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications
JY Yang, K Benaissa, D Crenshaw, B Williams, S Sridhar, J Ai, G Boselli, ...
Digest. International Electron Devices Meeting,, 667-670, 2002
29*2002
A flexible simulation model for system level ESD stresses with application to ESD design and troubleshooting
R Mertens, H Kunz, A Salman, G Boselli, E Rosenbaum
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, 1-6, 2012
252012
Efficient pnp characteristics of pMOS transistors in sub-0.13 µm ESD protection circuits
G Boselli, C Duvvury, V Reddy
2002 Electrical Overstress/Electrostatic Discharge Symposium, 260-269, 2002
252002
Overshoot-induced failures in forward-biased diodes: A new challenge to high-speed ESD design
F Farbiz, A Appaswamy, AA Salman, G Boselli
2013 IEEE International Reliability Physics Symposium (IRPS), 2B. 1.1-2B. 1.8, 2013
242013
Drain extended mos transistor having selectively silicided drain
AA Salman, F Farbiz, AC Appaswamy, JE Kunz, G Boselli
US Patent App. 13/441,318, 2013
232013
Mutual ballasting multi-finger bidirectional ESD device
AA Salman, F Farbiz, AM Concannon, G Boselli
US Patent 9,224,724, 2015
222015
Gate oxide failures due to anomalous stress from HBM ESD testers
C Duvvury, R Steinhoff, G Boselli, V Reddy, H Kunz, S Marum, R Cline
2004 Electrical Overstress/Electrostatic Discharge Symposium, 1-9, 2004
222004
Local ESD protection for low-capacitance applications
C Duvvury, G Boselli
US Patent 7,277,263, 2007
212007
Investigations on double-diffused MOS (DMOS) transistors under ESD zap conditions
G Boselli, S Meeuwsen, T Mouthaan, F Kuper
Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 …, 1999
201999
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