关注
Shanshi Huang
Shanshi Huang
HKUST-GZ
在 hkust-gz.edu.cn 的电子邮件经过验证
标题
引用次数
引用次数
年份
DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies
X Peng, S Huang, Y Luo, X Sun, S Yu
2019 IEEE international electron devices meeting (IEDM), 32.5. 1-32.5. 4, 2019
2582019
Compute-in-memory chips for deep learning: Recent trends and prospects
S Yu, H Jiang, S Huang, X Peng, A Lu
IEEE circuits and systems magazine 21 (3), 31-56, 2021
2002021
DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training
X Peng, S Huang, H Jiang, A Lu, S Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
1642020
15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips
JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020
1572020
Compute-in-memory with emerging nonvolatile-memories: Challenges and prospects
S Yu, X Sun, X Peng, S Huang
2020 ieee custom integrated circuits conference (cicc), 1-4, 2020
632020
CIMAT: A compute-in-memory architecture for on-chip training based on transpose SRAM arrays
H Jiang, X Peng, S Huang, S Yu
IEEE Transactions on Computers 69 (7), 944-954, 2020
482020
Analog-to-digital converter design exploration for compute-in-memory accelerators
H Jiang, W Li, S Huang, S Cosemans, F Catthoor, S Yu
IEEE Design & Test 39 (2), 48-55, 2021
362021
A two-way SRAM array based accelerator for deep neural network on-chip training
H Jiang, S Huang, X Peng, JW Su, YC Chou, WH Huang, TW Liu, R Liu, ...
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
332020
Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips
JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ...
IEEE Journal of Solid-State Circuits 57 (2), 609-624, 2021
292021
A 40nm analog-input ADC-free compute-in-memory RRAM macro with pulse-width modulation between sub-arrays
H Jiang, W Li, S Huang, S Yu
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
282022
A 40-nm MLC-RRAM compute-in-memory macro with sparsity control, on-chip write-verify, and temperature-independent ADC references
W Li, X Sun, S Huang, H Jiang, S Yu
IEEE Journal of Solid-State Circuits 57 (9), 2868-2877, 2022
272022
Secure-RRAM: A 40nm 16kb compute-in-memory macro with reconfigurability, sparsity control, and embedded security
W Li, S Huang, X Sun, H Jiang, S Yu
2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021
262021
XOR-CIM: Compute-in-memory SRAM architecture with embedded XOR encryption
S Huang, H Jiang, X Peng, W Li, S Yu
Proceedings of the 39th International Conference on Computer-Aided Design, 1-6, 2020
212020
A 40nm RRAM compute-in-memory macro featuring on-chip write-verify and offset-cancelling ADC references
W Li, X Sun, H Jiang, S Huang, S Yu
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC), 79-82, 2021
202021
MINT: Mixed-precision RRAM-based in-memory training architecture
H Jiang, S Huang, X Peng, S Yu
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
182020
CIMAT: A transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training
H Jiang, X Peng, S Huang, S Yu
Proceedings of the International Symposium on Memory Systems, 490-496, 2019
172019
Secure XOR-CIM engine: Compute-in-memory sram architecture with embedded xor encryption
S Huang, H Jiang, X Peng, W Li, S Yu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12 …, 2021
122021
New security challenges on machine learning inference engine: Chip cloning and model reverse engineering
S Huang, X Peng, H Jiang, Y Luo, S Yu
arXiv preprint arXiv:2003.09739, 2020
122020
Overcoming challenges for achieving high in-situ training accuracy with emerging memories
S Huang, X Sun, X Peng, H Jiang, S Yu
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
112020
ENNA: An efficient neural network accelerator design based on ADC-free compute-in-memory subarrays
H Jiang, S Huang, W Li, S Yu
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (1), 353-363, 2022
72022
系统目前无法执行此操作,请稍后再试。
文章 1–20