| DESIGN A LOW-COMPLEXITY VLSI ARCHITECTURE OF AHL MULTIPLIERS FOR FULLY HOMOMORPHIC ENCRYPTION MA NANDAM SANKEERTHANA, K. RAJKAMAL International journal for advanced research in science & technology 11 (3), 2021 | | 2021 |
| HIGH SPEED AREA EFFICIENT ARCHITECTURE OF THREE OPERAND BINARY ADDER USING MODIFIED CARRY SKIP ADDER DMA PRAKHYA SURYA BHARATH,Mr .B. SUBHAKARA RAO, Dr. K. RAJKAMAL The International journal of analytical and experimental modal analysis 8 (8 …, 2021 | | 2021 |
| A NOVEL LOW-POWER HIGH-SPEED CMOS COMPARATOR FOR PRECISE APPLICATIONS MA M. MOUNIKA NeuroQuantology 20 (20), 2020 | | 2020 |
| DESIGN AND IMPLEMENTATION OF FULL-SWING TECHNIQUE GDI BASED ALU USING MIXED LOGIC ADDER FUNCTIONALITY ML Dr. M. APPARAO, CH.PAPARAO Mukt Shabd Journal 9 (2347-3150), 2020 | | 2020 |
| IMPLEMENTATION OF DUAL DIGITAL WATERMARKING FOR COLOR IMAGE USING DCT AND DWT ML Dr. M. APPARAO, CH.PAPARAO Journal of Interdisciplinary Cycle Research 9 (0022-1945), 2019 | | 2019 |
| IMPLEMENTATION OF REVERSIBLE LOGIC BASED FAST FOURIER TRANSFORM FOR AREA EFFICIENT APPLICATIONS ML Dr. M. APPARAO, CH.PAPARAO The International journal of analytical and experimental modal analysis 9 …, 2019 | | 2019 |
| Design of Voltage Controlled Ring Oscillator for Higher Frequencies Using 90nm CMOS Technology MV RAO, M APPARAO | | 2017 |
| Design and Implementation of 5-Bit Low Power Dynamic Thermometer Encoder for Flash ADC RA VARDHAN, M APPARAO, D MANOGNA | | 2016 |
| A Novel Method for Low-Power and Area-Efficient Shift Register Using Pulsed Latches BA KUMAR, SCHK RAO, MA RAO | | 2016 |
| DESIGN A LOW-COMPLEXITY VLSI ARCHITECTURE OF AHL MULTIPLIERS FOR FULLY HOMOMORPHIC ENCRYPTION N SANKEERTHANA, K RAJKAMAL, M APPARAO | | |
