| A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology H Ghasemian, R Ghasemi, E Abiri, MR Salehi Microelectronics Journal 92, 104603, 2019 | 26 | 2019 |
| High efficient GDI-CNTFET-based approximate full adder for next generation of computer architectures A Sadeghi, R Ghasemi, H Ghasemian, N Shiri IEEE Embedded Systems Letters 15 (1), 33-36, 2022 | 15 | 2022 |
| A high precision high frequency VLSI multi-input min-max circuit based on WTA-LTA cells M Padash, A Khoei, K Hadidi, H Ghasemiyan 2011 International Conference on Electronic Devices, Systems and …, 2011 | 9 | 2011 |
| Two‐stage current‐reused variable‐gain low‐noise amplifier for X‐band receivers in 65 nm complementary metal oxide semiconductor technology MR Nikbakhsh, E Abiri, H Ghasemian, MR Salehi IET Circuits, Devices & Systems 12 (5), 630-637, 2018 | 8 | 2018 |
| Implement of a 10-bit 7.49 mW 1.2 GS/s DAC with a new segmentation method H Ghasemian, A hossein Ahmadi, E Abiri, MR Salehi AEU-International Journal of Electronics and Communications 131, 153554, 2021 | 6 | 2021 |
| A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology H Ghasemian, A Bahrami, E Abiri, MR Salehi Circuits, Systems, and Signal Processing, 1-25, 2021 | 6 | 2021 |
| An implementation of a new 11-bit 1.2 GS/s hybrid DAC with a noval 3-bit Sub-DAC H Ghasemian, A Ahmadi, E Abiri, MR Salehi Microelectronics Journal 103, 104872, 2020 | 5 | 2020 |
| A two stage variable-gain low-noise amplifier for X-band in 0.18 µm CMOS MR Nikbakhsh, E Abiri, H Ghasemian, MR Salehi Wireless Personal Communications 98, 173-187, 2018 | 5 | 2018 |
| Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology R Ghasemi, H Ghasemian, E Abiri, MR Salehi 2021 29th Iranian Conference on Electrical Engineering (ICEE), 159-164, 2021 | 4 | 2021 |
| Implement of Two New High-Speed Low-Power PFDs with Low Blind Zone and Dead Zone in 65nm CMOS Technology H Ghasemian, A Bahrami, E Abiri, MR Salehi 2020 28th Iranian Conference on Electrical Engineering (ICEE), 1-6, 2020 | 4 | 2020 |
| An analog multi-shaped and fully programmable twin-cell MFG structure in 65nm CMOS technology S Karami, H Ghasemian, E Abiri, MR Salehi 2019 27th Iranian Conference on Electrical Engineering (ICEE), 195-200, 2019 | 4 | 2019 |
| A novel 6GHz/573µwatt/30ps Dynamic Comparator with complementary differential input in 65nm CMOS Technology R Ghasemi, A Ahmadi, H Ghasemian, MR Salehi, E Abiri 2019 27th Iranian Conference on Electrical Engineering (ICEE), 236-242, 2019 | 4 | 2019 |
| A power-efficient high gain differential LNA in 0.18 µm CMOS technology for 400–900 MHz frequency range MR Nikbakhsh, E Abiri, S Salem, H Ghasemian 2017 Iranian Conference on Electrical Engineering (ICEE), 396-400, 2017 | 4 | 2017 |
| Design of a low power analog and multi-shaped fully programmable twin-cell membership function generator circuit in 65 nm CMOS technology H Ghasemian, S Karami, E Abiri, MR Salehi Circuits, Systems, and Signal Processing 40, 2-21, 2021 | 2 | 2021 |
| A Novel 10-bit 1.2 GS/s Hybrid Digital to Analog Converter with 8.4 mW Power Consumption A Ahmadi, H Ghasemian, E Abiri, R Ghasemi 2019 27th Iranian Conference on Electrical Engineering (ICEE), 163-168, 2019 | 2 | 2019 |
| Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits A Sadeghi, R Ghasemi, H Ghasemian, N Shiri Frontiers of Information Technology & Electronic Engineering 24 (4), 599-616, 2023 | | 2023 |
| 基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器 A SADEGHI, R GHASEMI, H GHASEMIAN, N SHIRI, AA SADEGHI, ... Frontiers 24 (4), 599-616, 2023 | | 2023 |
| Design and Implement of a Configurable ADS-B Out System Complying with RTCA DO-260 B and C A Alimadadi, P Ghasemian, N Peiravian, H Ghasemian | | |
