The vertical replacement-gate (VRG) MOSFET: A 50-nm vertical MOSFET with lithography-independent gate length JM Hergenrother, D Monroe, FP Klemens, A Komblit, GR Weber, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 261* | 1999 |
Bandgap and transport properties of Si/sub 1-x/Ge/sub x/by analysis of nearly ideal Si/Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors CA King, JL Hoyt, JF Gibbons IEEE transactions on electron devices 36 (10), 2093-2104, 1989 | 225 | 1989 |
Semiconductor devices with reduced active region defects and unique contacting schemes JD Bude, M Carroll, CA King US Patent 7,012,314, 2006 | 187 | 2006 |
Si/Si/sub 1-x/Ge/sub x/heterojunction bipolar transistors produced by limited reaction processing CA King, JL Hoyt, CM Gronet, JF Gibbons, M Scott, J Turner IEEE electron device letters 10 (2), 52-54, 1989 | 179 | 1989 |
Boron diffusion in strained epitaxial layers N Moriya, LC Feldman, HS Luftman, CA King, J Bevk, B Freer Physical review letters 71 (6), 883, 1993 | 167 | 1993 |
Reduction in misfit dislocation density by the selective growth of Si1− xGex/Si in small areas DB Noble, JL Hoyt, CA King, JF Gibbons, TI Kamins, MP Scott Applied physics letters 56 (1), 51-53, 1990 | 137 | 1990 |
Semiconductor devices with photoresponsive components and metal silicide light blocking structures CS Rafferty, C King US Patent 7,629,661, 2009 | 116 | 2009 |
Small-geometry, high-performance, Si-Si (1-x) Ge (x) heterojunction bipolar transistors TI Kamins, K Nauka, JB Kruger, JL Hoyt, CA King IEEE electron device letters 10, 503-505, 1989 | 112 | 1989 |
Semiconductor devices with reduced active region defects and unique contacting schemes JD Bude, M Carroll, CA King US Patent 7,297,569, 2007 | 99 | 2007 |
Growth of GeSi/Si strained‐layer superlattices using limited reaction processing CM Gronet, CA King, W Opyd, JF Gibbons, SD Wilson, R Hull Journal of applied physics 61 (6), 2407-2409, 1987 | 92 | 1987 |
Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry CA King, CS Rafferty US Patent 7,973,377, 2011 | 91 | 2011 |
Limited reaction processing: growth of Si1− xGex/Si for heterojunction bipolar transistor applications JL Hoyt, CA King, DB Noble, CM Gronet, JF Gibbons, MP Scott, ... Thin Solid Films 184 (1-2), 93-106, 1990 | 87 | 1990 |
Method for forming integrated circuit utilizing dual semiconductors CS Rafferty, C King US Patent 7,589,380, 2009 | 86 | 2009 |
IEEE Trans. Electron Devices CA King, JL Hoyt, JF Gibbons IEEE Trans. Electron Devices 36, 2093-2104, 1989 | 79 | 1989 |
Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry CA King, CS Rafferty US Patent 7,453,129, 2008 | 74 | 2008 |
Admittance spectroscopy measurements of band offsets in Si/Si1− xGex/Si heterostructures K Nauka, TI Kamins, JE Turner, CA King, JL Hoyt, JF Gibbons Applied physics letters 60 (2), 195-197, 1992 | 74 | 1992 |
Conservation of bond lengths in strained Ge-Si layers JC Woicik, CE Bouldin, MI Bell, JO Cross, DJ Tweet, BD Swanson, ... Physical Review B 43 (3), 2419, 1991 | 73 | 1991 |
Integrated circuit device with isolated circuit elements MR Frei, CA King, KK Ng, HT Weston, YH Xie US Patent 5,767,561, 1998 | 72 | 1998 |
Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions B Jalali-Farahani, CA King US Patent 5,834,800, 1998 | 63 | 1998 |
Changes in electrical device characteristics during the in situ formation of dislocations FM Ross, R Hull, D Bahnck, JC Bean, LJ Peticolas, CA King Applied physics letters 62 (12), 1426-1428, 1993 | 63 | 1993 |