| Block-wise concatenated BCH codes for NAND flash memories S Cho, D Kim, J Choi, J Ha IEEE Transactions on Communications 62 (4), 1164-1177, 2014 | 66 | 2014 |
| A configurable successive-cancellation list polar decoder using split-tree architecture Y Tao, SG Cho, Z Zhang IEEE Journal of Solid-State Circuits 56 (2), 612-623, 2020 | 58 | 2020 |
| Post-processing methods for improving coding gain in belief propagation decoding of polar codes S Sun, SG Cho, Z Zhang GLOBECOM 2017-2017 IEEE Global Communications Conference, 1-6, 2017 | 34 | 2017 |
| A 2048-neuron spiking neural network accelerator with neuro-inspired pruning and asynchronous network on chip in 40nm CMOS SG Cho, E Beigné, Z Zhang 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 29 | 2019 |
| Error patterns in belief propagation decoding of polar codes and their mitigation methods S Sun, SG Cho, Z Zhang 2016 50th Asilomar Conference on Signals, Systems and Computers, 1199-1203, 2016 | 22 | 2016 |
| Encoding, decoding, and multi-stage decoding circuits for concatenated BCH, and error correction circuit of flash memory device using the same JS Ha, SG Cho US Patent 9,166,626, 2015 | 19 | 2015 |
| Concatenated BCH codes for NAND flash memories S Cho, J Ha 2012 IEEE International Conference on Communications (ICC), 2611-2616, 2012 | 12 | 2012 |
| Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration W Tang, SG Cho, TT Hoang, J Botimer, WQ Zhu, CC Chang, CH Lu, J Zhu, ... IEEE Journal of Solid-State Circuits, 2023 | 6 | 2023 |
| Data processing block and data storage device including the same SG Cho US Patent 9,438,274, 2016 | 6 | 2016 |
| Data processing system and operating method thereof SG Cho US Patent App. 14/053,227, 2015 | 5 | 2015 |
| PETRA: A 22nm 6.97 TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA SG Cho, W Tang, C Liu, Z Zhang 2021 Symposium on VLSI Circuits, 1-2, 2021 | 4 | 2021 |
| A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS C Liu, SG Cho, Z Zhang IEEE Journal of Solid-State Circuits 53 (10), 2818-2827, 2018 | 4 | 2018 |
| A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS C Liu, SG Cho, Z Zhang 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 233-236, 2017 | 3 | 2017 |
| A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS Y Tao, SG Cho, Z Zhang 2019 Symposium on VLSI Circuits, C240-C241, 2019 | 2 | 2019 |
| Controller, semiconductor memory system and operating method thereof RHO Jun-Rye, SG Cho US Patent 9,825,651, 2017 | 2 | 2017 |
| Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload … W Tang, SG Cho, TT Hoang, J Botimer, WQ Zhu, CC Chang, CH Lu, J Zhu, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| Scalable, High-Performance Accelerators for Neural Network and Signal Processing: Logical and Physical Design Considerations SG Cho | | 2020 |
