关注
Karthik Ramanan
Karthik Ramanan
Principal Design Engineer, NXP Semiconductor
在 nxp.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
Charge pump with charge feedback and method of operation
TD Cook, JC Cunningham, K Ramanan
US Patent 7,948,301, 2011
272011
Configurable multistage charge pump using a supply detect scheme
K Ramanan, JC Cunningham, RJ Syzdek
US Patent 8,704,587, 2014
192014
Low power charge pump and method of operation
TD Cook, JC Cunningham, K Ramanan
US Patent 7,965,130, 2011
112011
Split-gate non-volatile memory (NVM) cell and device structure integration
CM Hong, K Ramanan
US Patent 8,932,925, 2015
102015
Negative charge pump regulation
JS Choy, GJ Muller, K Ramanan
US Patent 8,830,776, 2014
102014
Charge pump having ramp rate control
TD Cook, JC Cunningham, K Ramanan
US Patent 8,310,300, 2012
102012
Exponential charge pump
TD Cook, JC Cunningham, K Ramanan
US Patent 8,476,963, 2013
72013
Smart charge pump configuration for non-volatile memories
JC Cunningham, K Ramanan, RS Scouller, RJ Syzdek
US Patent 9,111,629, 2015
62015
Compensated hysteresis circuit
JT Williams, JC Cunningham, GJ Muller, K Ramanan
US Patent 8,829,964, 2014
62014
Charge pump for use with a synchronous load
TD Cook, JC Cunningham, K Ramanan
US Patent 8,040,700, 2011
52011
Variable input voltage charge pump
TD Cook, JC Cunningham, K Ramanan
US Patent 8,008,964, 2011
52011
Reference generation for voltage sensing in a resistive memory
K Ramanan, JS Choy, J Williams
US Patent 10,984,846, 2021
42021
Non-volatile memory with a select gate regulator circuit
JT Williams, JS Choy, K Ramanan
US Patent 10,796,741, 2020
42020
Oscillator with startup circuitry
GJ Muller, JC Cunningham, K Ramanan
US Patent 9,007,138, 2015
42015
Memory with one-time programmable (OTP) cells and reading operations thereof
JS Choy, JT Williams, K Ramanan, P Sanjeevarao, MMN Storms
US Patent 11,521,692, 2022
32022
Non-volatile memory with multiplexer transistor regulator circuit
P Sanjeevarao, JT Williams, K Ramanan, JS Choy
US Patent 11,250,898, 2022
32022
Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation
JS Choy, K Ramanan, P Sanjeevarao, JT Williams
US Patent 11,289,144, 2022
22022
A low power fast wakeup flash memory system for embedded SOCs
K Ramanan, J Williams
2017 IEEE International Conference on IC Design and Technology (ICICDT), 1-4, 2017
22017
Non-volatile memory with a well bias generation circuit
K Ramanan, JS Choy, JT Williams
US Patent 11,145,382, 2021
12021
Ratioless near-threshold level translator
JT Williams, JC Cunningham, K Ramanan
US Patent 9,209,810, 2015
12015
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