Charge pump with charge feedback and method of operation TD Cook, JC Cunningham, K Ramanan US Patent 7,948,301, 2011 | 27 | 2011 |
Configurable multistage charge pump using a supply detect scheme K Ramanan, JC Cunningham, RJ Syzdek US Patent 8,704,587, 2014 | 19 | 2014 |
Low power charge pump and method of operation TD Cook, JC Cunningham, K Ramanan US Patent 7,965,130, 2011 | 11 | 2011 |
Split-gate non-volatile memory (NVM) cell and device structure integration CM Hong, K Ramanan US Patent 8,932,925, 2015 | 10 | 2015 |
Negative charge pump regulation JS Choy, GJ Muller, K Ramanan US Patent 8,830,776, 2014 | 10 | 2014 |
Charge pump having ramp rate control TD Cook, JC Cunningham, K Ramanan US Patent 8,310,300, 2012 | 10 | 2012 |
Exponential charge pump TD Cook, JC Cunningham, K Ramanan US Patent 8,476,963, 2013 | 7 | 2013 |
Smart charge pump configuration for non-volatile memories JC Cunningham, K Ramanan, RS Scouller, RJ Syzdek US Patent 9,111,629, 2015 | 6 | 2015 |
Compensated hysteresis circuit JT Williams, JC Cunningham, GJ Muller, K Ramanan US Patent 8,829,964, 2014 | 6 | 2014 |
Charge pump for use with a synchronous load TD Cook, JC Cunningham, K Ramanan US Patent 8,040,700, 2011 | 5 | 2011 |
Variable input voltage charge pump TD Cook, JC Cunningham, K Ramanan US Patent 8,008,964, 2011 | 5 | 2011 |
Reference generation for voltage sensing in a resistive memory K Ramanan, JS Choy, J Williams US Patent 10,984,846, 2021 | 4 | 2021 |
Non-volatile memory with a select gate regulator circuit JT Williams, JS Choy, K Ramanan US Patent 10,796,741, 2020 | 4 | 2020 |
Oscillator with startup circuitry GJ Muller, JC Cunningham, K Ramanan US Patent 9,007,138, 2015 | 4 | 2015 |
Memory with one-time programmable (OTP) cells and reading operations thereof JS Choy, JT Williams, K Ramanan, P Sanjeevarao, MMN Storms US Patent 11,521,692, 2022 | 3 | 2022 |
Non-volatile memory with multiplexer transistor regulator circuit P Sanjeevarao, JT Williams, K Ramanan, JS Choy US Patent 11,250,898, 2022 | 3 | 2022 |
Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation JS Choy, K Ramanan, P Sanjeevarao, JT Williams US Patent 11,289,144, 2022 | 2 | 2022 |
A low power fast wakeup flash memory system for embedded SOCs K Ramanan, J Williams 2017 IEEE International Conference on IC Design and Technology (ICICDT), 1-4, 2017 | 2 | 2017 |
Non-volatile memory with a well bias generation circuit K Ramanan, JS Choy, JT Williams US Patent 11,145,382, 2021 | 1 | 2021 |
Ratioless near-threshold level translator JT Williams, JC Cunningham, K Ramanan US Patent 9,209,810, 2015 | 1 | 2015 |