| High Performance 14nm SOI FinFET CMOS Technology with 0.0174ìm2 embedded DRAM and 15 Levels of Cu Metallization International Electron Devices Meeting, 14-74, 2014 | 183* | 2014 |
| Gate stack for integrated circuit structure and method of forming same A Dasgupta, BG Moser, M Hasanuzzaman, MM Chowdhury, SA Khan, ... US Patent 9,748,235, 2017 | 17 | 2017 |
| Modeling germanium diffusion in superlattice structures M Hasanuzzaman, YM Haddara, AP Knights Journal of Applied Physics 105 (4), 043504, 2009 | 14 | 2009 |
| Modeling silicon–germanium interdiffusion by the vacancy exchange and interstitial mechanisms M Hasanuzzaman, YM Haddara Journal of Materials Science: Materials in Electronics 19 (6), 569-576, 2008 | 14 | 2008 |
| A mathematical model for void evolution in silicon by helium implantation and subsequent annealing process M Hasanuzzaman, YM Haddara, AP Knights Journal of Applied Physics 112 (6), 064302, 2012 | 9 | 2012 |
| Mapping of the mechanical response in Si/SiGe nanosheet device geometries NL Conal E. Murray, Hanfei Yan, Christian Lavoie, Jean Jordan-Sweet, Ajith ... Communications Engineering, 2022 | 7 | 2022 |
| Modeling vacancy injection from the silicon/silicon-nitride interface M Hasanuzzaman, YM Haddara Journal of Materials Science: Materials in Electronics 19 (4), 323-326, 2008 | 7 | 2008 |
| Methods of forming semiconductor fin with carbon dopant for diffusion control Y Ke, M Hasanuzzaman, BG Moser, SA Khan, SM Polvino US Patent 9,685,334, 2017 | 4 | 2017 |
| Formation of finFET junction S Ahmed, MM Chowdhury, A Dasgupta, M Hasanuzzaman, SA Khan, ... US Patent 9,431,485, 2016 | 4 | 2016 |
| FinFET Extension Regions M Hasanuzzaman, JB Johnson, KL Lee | 3 | 2015 |
| VOID EVOLUTION AND DEFECT INTERACTIONS IN SILICON AND SILICON GERMANIUM M Hasanuzzaman McMaster University, 2012 | 3 | 2012 |
| Void evolution in silicon under inert and dry oxidizing ambient annealing and the role of a Si1−xGex epilayer cap M Hasanuzzaman, YM Haddara, AP Knights Journal of Applied Physics 112 (5), 054909, 2012 | 2 | 2012 |
| High performance nanosheet technology optimized for 77 K R Bao, L Qin, J Frougier, S Suk, M Rabie, U Bajpai, A Chou, B Nechay, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | 1 | 2023 |
| CHARACTERISTICS OF PULSED LASER DEPOSITED N-CARBON/P-SILICON HETEROJUNCTION MZ Islam, M Alam, M Hasanuzzaman, S Mohammad 3rd International Conference on Electrical and Computer Engineering, Dhaka …, 2004 | 1 | 2004 |
| Producing stress in nanosheet transistor channels R Vega, R Robison, M Hasanuzzaman US Patent App. 18/086,303, 2024 | | 2024 |
| Coalesced fin to reduce fin bending AKMZR CHOWDHURY, SA Khan, J Shepard Jr, M Hasanuzzaman, ... US Patent App. 15/649,294, 2019 | | 2019 |
| Interaction of work function tuning and negative bias temperature instability for future nodes KZ Luigi Pantisano ⁎, Purushothaman Srinivasan, Taehoon Kim, Tao Chu, Merve ... Microelectronic Engineering 178, 258-261, 2017 | | 2017 |
| Role of a Si0.95Ge0.05 epilayer cap on boron diffusion in silicon under inert and dry oxidizing ambient annealing M Hasanuzzaman, YM Haddara, AP Knights Materials Science in Semiconductor Processing 48, 60-64, 2016 | | 2016 |
| Modeling germanium-silicon interdiffusion in silicon germanium/silicon superlattice structures M Hasanuzzaman, YM Haddara, AP Knights 2008 Nanotechnology Conference and Trade show, Boston, Massachusetts, USA 3 …, 2008 | | 2008 |
| Modeling voids in silicon M Hasanuzzaman, YM Haddara, AP Knights 2008 Nanotechnology Conference and Trade show, Boston, Massachusetts, USA 3 …, 2008 | | 2008 |
