| System-level simulation of hardware spiking neural network based on synaptic transistors and I&F neuron circuits S Hwang, H Kim, J Park, MW Kwon, MH Baek, JJ Lee, BG Park IEEE Electron Device Letters 39 (9), 1441-1444, 2018 | 52 | 2018 |
| Compact neuromorphic system with four-terminal Si-based synaptic devices for spiking neural networks J Park, MW Kwon, H Kim, S Hwang, JJ Lee, BG Park IEEE Transactions on Electron Devices 64 (5), 2438-2444, 2017 | 48 | 2017 |
| Integrated neuron circuit for implementing neuromorphic system with synaptic device JJ Lee, J Park, MW Kwon, S Hwang, H Kim, BG Park Solid-State Electronics 140, 34-40, 2018 | 38 | 2018 |
| Parallel Time Batching: Systolic-Array Acceleration of Sparse Spiking Neural Computation JJ Lee, W Zhang, P Li 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 33 | 2022 |
| Spike-train level direct feedback alignment: sidestepping backpropagation for on-chip training of spiking neural nets J Lee, R Zhang, W Zhang, Y Liu, P Li Frontiers in Neuroscience 14, 2020 | 33 | 2020 |
| Reconfigurable Dataflow Optimization for Spatiotemporal Spiking Neural Computation on Systolic Array Accelerators JJ Lee, P Li 2020 IEEE 38th International Conference on Computer Design (ICCD), 57-64, 2020 | 22 | 2020 |
| Analog Complementary Metal–Oxide–Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks S Hwang, JJ Lee, MW Kwon, MH Baek, T Jang, J Chang, JH Lee, BG Park Journal of nanoscience and nanotechnology 20 (5), 3117-3122, 2020 | 15 | 2020 |
| A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition Y Wang, JJ Lee, Y Ding, P Li 2020 21st International Symposium on Quality Electronic Design (ISQED), 370-376, 2020 | 11 | 2020 |
| Systolic-Array Spiking Neural Accelerators with Dynamic Heterogeneous Voltage Regulation JJ Lee, J Chen, W Zhang, P Li 2021 International Joint Conference on Neural Networks (IJCNN), 1-7, 2021 | 3 | 2021 |
| Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices MH Baek, T Jang, H Kim, J Park, MW Kwon, S Hwang, S Kim, JJ Lee, ... Japanese Journal of Applied Physics 58 (10), 101004, 2019 | 3 | 2019 |
| Neuron Circuit P ByungGook, JJ Lee US Patent App. 16/509,399, 2020 | 1 | 2020 |
| Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors J Park, H Kim, MW Kwon, S Hwang, MH Baek, JJ Lee, T Jang, BG Park Journal of Semiconductor Technology and Science 17 (2), 210-215, 2017 | 1 | 2017 |
| Gated-thyristor DRAM cell with pillar channel structure H Kim, MW Kwon, MH Baek, S Hwang, S Kim, T Jang, JJ Lee, HM Kim, ... 2017 Silicon Nanoelectronics Workshop (SNW), 71-72, 2017 | | 2017 |
| Implementation of inhibitory operation in neuromorphic system JJ Lee, MW Kwon, H Kim, S Hwang, BG Park 2017 Silicon Nanoelectronics Workshop (SNW), 113-114, 2017 | | 2017 |
