| Machine intelligence for efficient test pattern generation S Roy, SK Millican, VD Agrawal 2020 IEEE International Test Conference (ITC), 1-5, 2020 | 26 | 2020 |
| Applying neural networks to delay fault testing: Test point insertion and random circuit training S Millican, Y Sun, S Roy, V Agrawal 2019 IEEE 28th Asian Test Symposium (ATS), 13-135, 2019 | 26 | 2019 |
| Improved random pattern delay fault coverage using inversion test points S Roy, B Stiene, SK Millican, VD Agrawal 2019 IEEE 28th North Atlantic Test Workshop (NATW), 206-211, 2019 | 26 | 2019 |
| Special session–machine learning in test: A survey of analog, digital, memory, and rf integrated circuits S Roy, SK Millican, VD Agrawal 2021 IEEE 39th VLSI Test Symposium (VTS), 1-14, 2021 | 25 | 2021 |
| Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator S Roy, SK Millican, VD Agrawal Proceedings of the IEEE International Conference on VLSI Design …, 2021 | 25 | 2021 |
| Principal component analysis in machine intelligence-based test generation S Roy, SK Millican, VD Agrawal 2021 IEEE Microelectronics Design & Test Symposium (MDTS), 1-6, 2021 | 17 | 2021 |
| Unsupervised Learning in Test Generation for Digital Integrated Circuits S Roy, SK Millican, VD Agrawal Proceedings of the IEEE European Test Symposium, Belgium, 2021 | 13 | 2021 |
| Improved pseudo-random fault coverage through inversions: a study on test point architectures S Roy, B Stiene, SK Millican, VD Agrawal Journal of Electronic Testing 36, 123-133, 2020 | 13 | 2020 |
| Toward zero backtracks in test pattern search algorithms with machine learning S Roy Auburn University, 2021 | 9 | 2021 |
| Multi-heuristic machine intelligence guidance in automatic test pattern generation S Roy, SK Millican, VD Agrawal 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS), 1-6, 2022 | 8 | 2022 |
| An amalgamated testability measure derived from machine intelligence S Roy, VD Agrawal 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | 3 | 2024 |
| System and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuits S Millican, Y Sun, S Roy, VD Agrawal US Patent App. 17/226,950, 2021 | 2 | 2021 |
| A Survey and Recent Advances: Machine Intelligence in Electronic Testing S Roy, SK Millican, VD Agrawal Journal of Electronic Testing, 1-20, 2024 | | 2024 |
| Applying Artificial Neural Networks to Test-point Insertion: Delay Fault Coverage and Training Circuit Generation S Millican, Y Sun, S Roy, V Agrawal IEEE International Test Conference, Washington DC, 2019 | | 2019 |
| Design and Implementation of an on-Chip Test Architecture for a Homogeneous Many-Core System. S Roy Technical University of Dresden, Germany, 2018 | | 2018 |
| Effective ATPG with Hierarchical DFT Methodology for SOC A Shankar, S Shareef, S Roy Synopsys Users Group, Bangalore, India, 2013 | | 2013 |
Vishwani Agrawalprofessor of electrical engineering在 eng.auburn.edu 的电子邮件经过验证
Vishwani Agrawalprofessor of electrical engineering在 eng.auburn.edu 的电子邮件经过验证