16.5 DynaPlasia: An eDRAM in-memory-computing-based reconfigurable spatial accelerator with triple-mode cell for dynamic resource switching S Kim, Z Li, S Um, W Jo, S Ha, J Lee, S Kim, D Han, HJ Yoo 2023 IEEE International Solid-State Circuits Conference (ISSCC), 256-258, 2023 | 28 | 2023 |
A 36.2 dB high SNR and PVT/leakage-robust eDRAM computing-in-memory macro with segmented BL and reference cell array S Ha, S Kim, D Han, S Um, HJ Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 69 (5), 2433-2437, 2022 | 28 | 2022 |
DynaPlasia: An eDRAM in-memory computing-based reconfigurable spatial accelerator with triple-mode cell S Kim, Z Li, S Um, W Jo, S Ha, J Lee, S Kim, D Han, HJ Yoo IEEE Journal of Solid-State Circuits, 2023 | 12 | 2023 |
Scaling-CIM: An eDRAM-based in-memory-computing accelerator with dynamic-scaling ADC for SQNR-boosting and layer-wise adaptive bit-truncation S Kim, S Um, W Jo, J Lee, S Ha, Z Li, HJ Yoo 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 6 | 2023 |
Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation S Kim, S Um, W Jo, J Lee, S Ha, Z Li, HJ Yoo IEEE Journal of Solid-State Circuits, 2024 | 4 | 2024 |
Cache-PIM: An ECC-compatible eDRAM-PIM for Last-Level Cache with Resolution-aware Single-Cycle Voting S Ha, S Um, S Kim, K Sohn, HJ Yoo 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 573-576, 2024 | 1 | 2024 |
A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-Computing S Whang, S Um, S Ha, HJ Yoo 2024 21st International SoC Design Conference (ISOCC), 117-118, 2024 | | 2024 |
NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator S Kim, Z Li, S Um, W Jo, S Ha, S Kim, HJ Yoo 2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2024 | | 2024 |
(A) high SNR and PVT/leakage-robust eDRAM computing-in-memory macro S Ha 한국과학기술원, 2022 | | 2022 |