| Quaternary CMOS combinational logic circuits VP KS, KS Gurumurthy 2009 International Conference on Information and Multimedia Technology, 538-542, 2009 | 56 | 2009 |
| Arithmetic operations in multi-valued logic V Patel, KS Gurumurthy arXiv preprint arXiv:1003.5442, 2010 | 53 | 2010 |
| Design of high performance quaternary adders KS Vasundara Patel, KS Gurumurthy International Journal of Computer Theory and Engineering 2 (6), 944-952, 2010 | 42* | 2010 |
| Multi-valued logic addition and multiplication in Galois field VP KS, KS Gurumurthy 2009 International Conference on Advances in Computing, Control, and …, 2009 | 24 | 2009 |
| A novel design and implementation of multi-valued logic arithmetic full adder circuit using CNTFET LS Phanindra, MN Rajath, V Rakesh, KSV Patel 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 16 | 2016 |
| Quaternary sequential circuits VP KS, K Gurumurthy IJCSNS International Journal of Computer Science and Network Security 10 (7 …, 2010 | 14 | 2010 |
| Static Random Access Memory Using Quaternary Latch P Vasundara, KS Gurumurthy, S Vinay International Journal of Engineering Science and Technology 2 (11), 6371-6379, 2010 | 11 | 2010 |
| Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques VPKSR Tulasi Naga Jyothi Kolanti Inter national Journal of Circuit Theory and Application. 48 (12), 2041-2055, 2020 | 8* | 2020 |
| Implementation of 5–32 address decoders for SRAM memory in 180nm technology BN Bagamma, KSV Patel, P Ravi 2017 International Conference on Electrical, Electronics, Communication …, 2017 | 7 | 2017 |
| A novel, dynamic data dissemination [D3] technique for congestion avoidance/control in high speed wireless multimedia sensor networks US Visweswaraiya, KS Gurumurthy 2013 Fifth International Conference on Computational Intelligence, Modelling …, 2013 | 7 | 2013 |
| Power Reduction in FinFET Half Adder using SVL Technique in 32nm Technology MN Satish, KSV Patel 2019 4th MEC International Conference on Big Data and Smart City (ICBDSC), 1-5, 2019 | 6 | 2019 |
| A novel design of ternary level SRAM cell using CNTFET S Niranjan, S Sandesh, VP KS 2018 International Conference on Networking, Embedded and Wireless Systems …, 2018 | 6 | 2018 |
| Comparative Study of gm/ID Methodology for Low-Power Applications NAMM Krishnan, KS Vasundhara Patel, M Jadhav Emerging Research in Electronics, Computer Science and Technology …, 2019 | 5 | 2019 |
| Design of ternary subtractor using multiplexers TNJ Kolanti, VP KS Circuit World 49 (3), 315-327, 2023 | 4 | 2023 |
| Quaternary Digital Circuits Design Using Carbon Nano Tube Fets TNJ Kolanti, PKS Vasundara 2018 International Conference on Networking, Embedded and Wireless Systems …, 2018 | 4 | 2018 |
| Design of SPA decoder for CDMA applications A Rajagopal, K Karibasappa, KSV Patel 2017 International Conference on Intelligent Computing and Control (I2C2), 1-6, 2017 | 4 | 2017 |
| Schmitt trigger based SRAM using finfet technology-shorted gate mode KS Vasundara Patel, HN Bhushan, KG Gadag, BN Nischal Prasad, ... World Academy of Science, Engineering and Technology International Journal …, 2014 | 4 | 2014 |
| A Novel Design and Implementation of Imaging Chip Using AXI Protocol for MPSOC on FPGA HR Archana, KS Vasundara Patel Intelligent Systems in Cybernetics and Automation Control Theory 2, 44-57, 2019 | 3 | 2019 |
| An investigation towards effectiveness in image enhancement process in mpsoc HR Archana, VP KS International Journal of Electrical and Computer Engineering 8 (2), 963, 2018 | 3 | 2018 |
| Comparative Analysis of Digital Circuits Using 16 nm FinFET and HKMG PTM Models SM Nachappa, AS Jeevitha, KS Vasundara Patel Advances in Information and Communication Networks: Proceedings of the 2018 …, 2019 | 2 | 2019 |
Jyothi KolantiPhD Scholar, BMSCE在 bmsce.ac.in 的电子邮件经过验证
