| Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET GP Lansbergen, R Rahman, CJ Wellard, I Woo, J Caro, N Collaert, ... Nature Physics 4 (8), 656-661, 2008 | 447 | 2008 |
| Analysis of the parasitic S/D resistance in multiple-gate FETs A Dixit, A Kottantharayil, N Collaert, M Goodwin, M Jurczak, K De Meyer IEEE Transactions on Electron Devices 52 (6), 1132-1140, 2005 | 438 | 2005 |
| Transport spectroscopy of a single dopant in a gated silicon nanowire H Sellier, GP Lansbergen, J Caro, S Rogge, N Collaert, I Ferain, ... Physical Review Letters 97 (20), 206805, 2006 | 359 | 2006 |
| Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification B Kaczer, V Arkhipov, R Degraeve, N Collaert, G Groeseneken, ... 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005 | 226 | 2005 |
| Vertical GAAFETs for the ultimate CMOS scaling D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ... IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015 | 207 | 2015 |
| Review of FINFET technology M Jurczak, N Collaert, A Veloso, T Hoffmann, S Biesemans 2009 IEEE international SOI conference, 1-4, 2009 | 199 | 2009 |
| Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective V Subramanian, B Parvais, J Borremans, A Mercha, D Linten, P Wambacq, ... IEEE Transactions on Electron Devices 53 (12), 3071-3079, 2006 | 191 | 2006 |
| Integrated semiconductor fin device and a method for manufacturing such device N Collaert, K De Meyer US Patent 6,974,729, 2005 | 171 | 2005 |
| Fabrication and Analysis of a Heterojunction Line Tunnel FET AM Walke, A Vandooren, R Rooyackers, D Leonelli, A Hikavyy, R Loo, ... IEEE Transactions on Electron Devices 61 (3), 707-715, 2014 | 144 | 2014 |
| Multi-gate devices for the 32 nm technology node and beyond N Collaert, A De Keersgieter, A Dixit, I Ferain, LS Lai, D Lenoble, ... Solid-State Electronics 52 (9), 1291-1296, 2008 | 130 | 2008 |
| FinFET analogue characterization from DC to 110 GHz D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ... Solid-State Electronics 49 (9), 1488-1496, 2005 | 127 | 2005 |
| InGaAs gate-all-around nanowire devices on 300mm Si substrates N Waldron, C Merckling, L Teugels, P Ong, SAU Ibrahim, F Sebaai, ... IEEE Electron Device Letters 35 (11), 1097-1099, 2014 | 118 | 2014 |
| Heteroepitaxy of InP on Si (001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering C Merckling, N Waldron, S Jiang, W Guo, N Collaert, M Caymax, ... Journal of Applied Physics 115 (2), 2014 | 118 | 2014 |
| Impact of fin width on digital and analog performances of n-FinFETs V Subramanian, A Mercha, B Parvais, J Loo, C Gustin, M Dehan, ... Solid-State Electronics 51 (4), 551-559, 2007 | 115 | 2007 |
| An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates N Waldron, C Merckling, W Guo, P Ong, L Teugels, S Ansar, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 109 | 2014 |
| Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip R Huys, D Braeken, D Jans, A Stassen, N Collaert, J Wouters, J Loo, ... Lab on a Chip 12 (7), 1274-1280, 2012 | 108 | 2012 |
| Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography MJH Van Dal, N Collaert, G Doornbos, G Vellianitis, G Curatola, ... 2007 IEEE symposium on VLSI technology, 110-111, 2007 | 103 | 2007 |
| Tall triple-gate devices with TiN/HfO/sub 2/gate stack N Collaert, M Demand, I Ferain, J Lisoni, R Singanamalla, P Zimmerman, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 108-109, 2005 | 103 | 2005 |
| Direct measurement of top and sidewall interface trap density in SOI FinFETs G Kapila, B Kaczer, A Nackaerts, N Collaert, GV Groeseneken IEEE electron device letters 28 (3), 232-234, 2007 | 102 | 2007 |
| BJT effect analysis in p-and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application M Galeti, M Rodrigues, JA Martino, N Collaert, E Simoen, M Aoulaiche, ... IEEE 2011 International SOI Conference, 1-2, 2011 | 94 | 2011 |
Aaron TheanNational University of Singapore在 nus.edu.sg 的电子邮件经过验证
