| Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for … CP Roth, R Kolagotla, J Fridman US Patent 6,948,056, 2005 | 397 | 2005 |
| VLSI implementation of 350 MHz 0.35 µm 8 bit merged squarer RK Kolagotla, WR Griesbach, HR Srinivas Electronics Letters 34 (1), 47-48, 1998 | 91 | 1998 |
| Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms KJR Liu, CT Chiu, RK Kolagotla, JF Jala IEEE transactions on circuits and systems for video technology 4 (2), 168-180, 1994 | 88 | 1994 |
| Design and implementation of a 16 by 16 low-power two's complement multiplier A Goldovsky, B Patel, M Schulte, R Kolagotla, H Srinivas, G Burns 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 345-348, 2000 | 58 | 2000 |
| High performance dual-MAC DSP architecture RK Kolagotla, J Fridman, BC Aldrich, MM Hoffman, WC Anderson, ... IEEE Signal Processing Magazine 19 (4), 42-53, 2002 | 44 | 2002 |
| Data synchronization for a test access port CP Roth, RP Singh, R Kolagotla, T Dinh US Patent 7,168,032, 2007 | 42 | 2007 |
| Single-step processing and selecting debugging modes CP Roth, RP Singh, T Dingh, R Kolagotla, M Hoffman, R Rivin US Patent 6,986,026, 2006 | 41 | 2006 |
| Shared correlator system and method for direct-sequence CDMA demodulation GF Burns, RK Kolagotla US Patent 6,470,000, 2002 | 37 | 2002 |
| System having a configurable cache/SRAM memory HS Ramagopal, DB Witt, M Allen, M Syed, R Kolagotla, LA Booth Jr, ... US Patent 6,446,181, 2002 | 34 | 2002 |
| Method and apparatus to compact trace in a trace buffer R Peri, C Chrulski, R Kolagotla US Patent App. 10/814,374, 2005 | 33 | 2005 |
| VLSI implementation of a 200-MHz 16/spl times/16 left-to-right carry-free multiplier in 0.35/spl mu/m CMOS technology for next-generation DSPs RK Kolagotla, HR Srinivas, GF Burns Proceedings of CICC 97-Custom Integrated Circuits Conference, 469-472, 1997 | 31 | 1997 |
| Method, apparatus, system for representing, specifying and using deadlines DF Cutter, B Fanning, R Nagarajan, R Iyer, QT Le, R Kolagotla, ... US Patent 9,563,579, 2017 | 27 | 2017 |
| Modulo address generator with precomputed comparison and correction terms RK Kolagotla, MK Prasad US Patent 6,049,858, 2000 | 26 | 2000 |
| DSP unit for multi-level global accumulation BC Aldrich, R Kolagotla US Patent 6,820,102, 2004 | 25 | 2004 |
| Digital communication system for high-speed complex correlation TW Baker, RA Cesari, RK Kolagotla US Patent 6,163,563, 2000 | 25 | 2000 |
| High speed module address generator RK Kolagotla, MK Prasad US Patent 5,983,333, 1999 | 24 | 1999 |
| Method for extending the local memory address space of a processor JG Revilla, RK Kolagotla US Patent 7,174,429, 2007 | 22 | 2007 |
| Squarer with diagonal row merged into folded partial product array WR Griesbach, RK Kolagotla US Patent 6,018,758, 2000 | 21 | 2000 |
| VLSI implementation of a tree searched vector quantizer RK Kolagotla, SS Yu, JF JaJa IEEE transactions on signal processing 41 (2), 901-905, 1993 | 21 | 1993 |
| Scan-bypass architecture without additional external latches PS Gillis, RK Kolagotla, DA Miller, M Noack, SF Oakland, CJ Rebeor, ... US Patent 5,925,143, 1999 | 19 | 1999 |
