Design methodology for voltage-scaled clock distribution networks C Sitik, W Liu, B Taskin, E Salman IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016 | 34 | 2016 |
Enhanced level shifter for multi-voltage operation W Liu, E Salman, C Sitik, B Taskin 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1442-1445, 2015 | 17 | 2015 |
SLECTS: Slew-driven clock tree synthesis W Liu, C Sitik, E Salman, B Taskin, S Sundareswaran, B Huang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 864-874, 2019 | 16 | 2019 |
A novel static D-flip-flop topology for low swing clocking M Rathore, W Liu, E Salman, C Sitik, B Taskin Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015 | 9 | 2015 |
Clock skew scheduling in the presence of heavily gated clock networks W Liu, E Salman, C Sitik, B Taskin Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 283-288, 2015 | 9 | 2015 |
Exploiting useful skew in gated low voltage clock trees W Liu, E Salman, C Sitik, B Taskin 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2595-2598, 2016 | 4 | 2016 |
Slew-driven clock tree synthesis WC Liu, E Salman, AC Sitik, B Taskin US Patent 10,338,633, 2019 | 3 | 2019 |
Low voltage clock tree synthesis with local gate clusters C Sitik, W Liu, B Taskin, E Salman Proceedings of the 2019 Great Lakes Symposium on VLSI, 99-104, 2019 | 2 | 2019 |
Circuits and algorithms to facilitate low swing clocking in nanoscale technologies W Liu, E Salman, C Sitik, B Taskin, S Sundareswaran, B Huang Proceedings of the Semiconductor Research Corporation (SRC) TECHCON, 2015 | 2 | 2015 |
Low Voltage Clocking Methodologies for Nanoscale ICs W Liu State University of New York at Stony Brook, 2018 | | 2018 |
Slew-Driven Clock Tree Synthesis (SLECTS) Methodology to Facilitate Low Voltage Clocking W Liu, C Sitik, E Salman, B Taskin, S Sundareswaran, B Huang Semiconductor Research Corporation (SRC) Technology Conference (TECHCON), 2016 | | 2016 |