| High-speed VLSI architectures for the AES algorithm X Zhang, KK Parhi IEEE transactions on very large scale integration (VLSI) systems 12 (9), 957-967, 2004 | 627 | 2004 |
| Implementation approaches for the advanced encryption standard algorithm X Zhang, KK Parhi IEEE Circuits and systems Magazine 2 (4), 24-46, 2002 | 213 | 2002 |
| Wireless security and cryptography: specifications and implementations N Sklavos, M Manninger, X Zhang, O Koufopavlou, V Hassler, P Kitsos, ... CRC press, 2017 | 172 | 2017 |
| On the optimum constructions of composite field for the AES algorithm X Zhang, KK Parhi IEEE Transactions on circuits and systems II: express briefs 53 (10), 1153-1157, 2006 | 141 | 2006 |
| Error correction for multi-level NAND flash memory using Reed-Solomon codes B Chen, X Zhang, Z Wang 2008 IEEE Workshop on Signal Processing Systems, 94-99, 2008 | 132 | 2008 |
| Reduced-complexity decoder architecture for non-binary LDPC codes X Zhang, F Cai IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (7 …, 2010 | 109 | 2010 |
| High-speed architectures for parallel long BCH encoders X Zhang, KK Parhi Proceedings of the 14th ACM Great Lakes symposium on VLSI, 1-6, 2004 | 106 | 2004 |
| Reliability-driven ECC allocation for multiple bit error resilience in processor cache S Paul, F Cai, X Zhang, S Bhunia IEEE Transactions on Computers 60 (1), 20-34, 2010 | 74 | 2010 |
| Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes X Zhang, F Cai IEEE Transactions on Circuits and Systems I: Regular Papers 58 (2), 402-414, 2010 | 72 | 2010 |
| Low-complexity reliability-based message-passing decoder architectures for non-binary LDPC codes X Zhang, F Cai, S Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (11 …, 2011 | 67 | 2011 |
| VLSI architectures for modern error-correcting codes X Zhang Crc Press, 2016 | 66 | 2016 |
| Backward interpolation architecture for algebraic soft-decision Reed–Solomon decoding J Zhu, X Zhang, Z Wang IEEE transactions on very large scale integration (VLSI) systems 17 (11 …, 2009 | 60 | 2009 |
| Reduced-complexity column-layered decoding and implementation for LDPC codes Z Cui, Z Wang, X Zhang IET communications 5 (15), 2177-2186, 2011 | 56 | 2011 |
| Relaxed min-max decoder architectures for nonbinary low-density parity-check codes F Cai, X Zhang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (11 …, 2012 | 54 | 2012 |
| Parity check matrix optimization and selection for iterative decoding J Jiang, T Tian, R Krishnamoorthi, X Zhang, A Mantravadi, K Mukkavilli US Patent 8,443,255, 2013 | 41 | 2013 |
| A low-complexity three-error-correcting BCH decoder for optical transport network X Zhang, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 59 (10), 663-667, 2012 | 41 | 2012 |
| Fast factorization architecture in soft-decision Reed-Solomon decoding X Zhang, KK Parhi IEEE transactions on very large scale integration (VLSI) systems 13 (4), 413-426, 2005 | 41 | 2005 |
| Factorization-free low-complexity Chase soft-decision decoding of Reed-Solomon codes J Zhu, X Zhang 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2677-2680, 2009 | 38 | 2009 |
| A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA, and GPU architectures O Ferraz, S Subramaniyan, R Chinthala, J Andrade, JR Cavallaro, ... IEEE Communications Surveys & Tutorials 24 (1), 524-556, 2021 | 35 | 2021 |
| Generalized SAT-attack-resistant logic locking J Zhou, X Zhang IEEE Transactions on Information Forensics and Security 16, 2581-2592, 2021 | 31 | 2021 |
